JAJSJT8C May   2020  – June 2021 TPS543620


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Enable and Adjustable UVLO
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. Internal PWM Oscillator Frequency
        2. Loss of Synchronization
        3. Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Ramp Amplitude Selection
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Mode Pin
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Current Protection
        1. Positive Inductor Current Protection
        2. Negative Inductor Current Protection
      11. 7.3.11 Output Overvoltage and Undervoltage Protection
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Output Voltage Discharge
      14. 7.3.14 Low-Side MOSFET Resistance Scaling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode during Soft Start
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. Design Requirements
        2. Detailed Design Procedure
          1.  Switching Frequency
          2.  Output Inductor Selection
          3.  Output Capacitor
          4.  Input Capacitor
          5.  Adjustable Undervoltage Lockout
          6.  Output Voltage Resistors Selection
          7.  Bootstrap Capacitor Selection
          8.  BP5 Capacitor Selection
          9.  PGOOD Pullup Resistor
          10. Current Limit Selection
          11. Soft-Start Time Selection
          12. Ramp Selection and Control Loop Stability
          13. MODE Pin
        3. Application Curves
      2. 8.2.2 1.0-V Output, 1.5-MHz Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      3. 8.2.3 3.3-V Output, 1.0-MHz Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      4. 8.2.4 1.8-V Output, 1.0-MHz Typical Application
        1. Design Requirements
        2. Detailed Design Procedure
      5. 8.2.5 5.0-V Output, 1.0-MHz Typical Application
        1. Design Requirements
        2. Detailed Design Procedure
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information


Ramp Selection and Control Loop Stability

The MODE pin is used to select between three different ramp settings. The most optimal ramp setting depends on VOUT, fSW, LOUT, and COUT. To get started, calculate LC double pole frequency using Equation 19. The ratio between fSW and fLC should then be calculated. Based on this ratio and the output voltage, the recommended ramp setting should be selected using Figure 8-3. With a 1-V output, the 1-pF ramp is recommended for ratios between approximately 35 and 58, the 2-pF ramp is recommended for ratios between approximately 58 and 86, and the 4-pF ramp is recommended for ratios greater than approximately 86. In general, it is best to use the largest ramp capacitor the design will support. Increasing the ramp capacitor improves transient response but can reduce stability margin or increase on-time jitter.

For this design, fLC is 17.5 kHz and the ratio is 57 which is on the border of the 1-pF and 2-pF ramp settings. Through bench evaluation, it was found that the design had sufficient stability margin with the 2-pF ramp so this setting was selected for the best transient response. The recommended ramp settings given by Figure 8-3 include margin to account for potential component tolerances and variations across operating conditions so it is possible to use a higher ramp setting as shown in this example.

Equation 19. GUID-21309C6E-03E1-4D2C-B5D6-39CDB0E102AF-low.gif
GUID-4C5009A0-FB5F-46D0-9201-3A9A5172AF42-low.gifFigure 8-3 Recommended Ramp Settings

Use a feedforward capacitor (CFF) in parallel with the upper feedback resistor (RFBT) to add a zero into the control loop to provide phase boost. Include a placeholder for this capacitor as the zero it provides can be required to meet phase margin requirements. This capacitor also adds a pole at a higher frequency than the zero. The pole and zero frequency are not independent so as a result, once the zero location is chosen, the pole is fixed as well. The zero is placed at 1/4 the fSW by calculating the value of CFF with Equation 20. The calculated value is 128 pF — round this down to the closest standard value of 120 pF.

Using bench measurements of the AC response, the feedforward capacitor for this example design was increased to 180 pF to improve the transient response.

Equation 20. GUID-213D23D0-F680-4D59-B009-678511C8025E-low.gif

It is possible to use larger feedforward capacitors to further improve the transient response but take care to ensure there is a minimum of -9-dB gain margin in all operating conditions. The feedforward capacitor injects noise on the output into the FB pin. This added noise can result in increased on-time jitter at the switching node. Too little gain margin can cause a repeated wide and narrow pulse behavior. Adding a 100-Ω resistor in series with the feedforward capacitor can help reduce the impact of noise on the FB pin in case of non-ideal PCB layout. The value of this resistor must be kept small as larger values bring the feedforward pole and zero closer together degrading the phase boost the feedforward capacitor provides.

When using higher ESR output capacitors, such as polymer or tantalum, their ESR zero (fESR) should be accounted for. The ESR zero can be calculated using Equation 21. If the ESR zero frequency is less than the estimated bandwidth of 1/10th the fSW, it can affect the gain margin and phase margin. A series R-C from the FB pin to ground can be used to add a pole into the control loop if necessary. All ceramic capacitors are used in this design so the effect of the ESR zero is ignored.

Equation 21. GUID-E947FD55-DF4E-431B-8C53-2090FAB87637-low.gif