JAJSJT8C May   2020  – June 2021 TPS543620

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN Pins and VIN UVLO
      2. 7.3.2  Enable and Adjustable UVLO
      3. 7.3.3  Adjusting the Output Voltage
      4. 7.3.4  Switching Frequency Selection
      5. 7.3.5  Switching Frequency Synchronization to an External Clock
        1. 7.3.5.1 Internal PWM Oscillator Frequency
        2. 7.3.5.2 Loss of Synchronization
        3. 7.3.5.3 Interfacing the SYNC/FSEL Pin
      6. 7.3.6  Ramp Amplitude Selection
      7. 7.3.7  Soft Start and Prebiased Output Start-up
      8. 7.3.8  Mode Pin
      9. 7.3.9  Power Good (PGOOD)
      10. 7.3.10 Current Protection
        1. 7.3.10.1 Positive Inductor Current Protection
        2. 7.3.10.2 Negative Inductor Current Protection
      11. 7.3.11 Output Overvoltage and Undervoltage Protection
      12. 7.3.12 Overtemperature Protection
      13. 7.3.13 Output Voltage Discharge
      14. 7.3.14 Low-Side MOSFET Resistance Scaling
    4. 7.4 Device Functional Modes
      1. 7.4.1 Forced Continuous-Conduction Mode
      2. 7.4.2 Discontinuous Conduction Mode during Soft Start
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 1.0-V Output, 1-MHz Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Switching Frequency
          2. 8.2.1.2.2  Output Inductor Selection
          3. 8.2.1.2.3  Output Capacitor
          4. 8.2.1.2.4  Input Capacitor
          5. 8.2.1.2.5  Adjustable Undervoltage Lockout
          6. 8.2.1.2.6  Output Voltage Resistors Selection
          7. 8.2.1.2.7  Bootstrap Capacitor Selection
          8. 8.2.1.2.8  BP5 Capacitor Selection
          9. 8.2.1.2.9  PGOOD Pullup Resistor
          10. 8.2.1.2.10 Current Limit Selection
          11. 8.2.1.2.11 Soft-Start Time Selection
          12. 8.2.1.2.12 Ramp Selection and Control Loop Stability
          13. 8.2.1.2.13 MODE Pin
        3. 8.2.1.3 Application Curves
      2. 8.2.2 1.0-V Output, 1.5-MHz Application
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
      3. 8.2.3 3.3-V Output, 1.0-MHz Application
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 1.8-V Output, 1.0-MHz Typical Application
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
      5. 8.2.5 5.0-V Output, 1.0-MHz Typical Application
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Detailed Design Procedure
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
      1. 10.2.1 Thermal Performance
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

TJ = –40 °C to +150°C, VVIN = 4 V - 18 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE
IQ(VIN) VIN operating non-switching supply current VEN = 1.3 V, VFB = 550 mV, VVIN = 12 V, 1 MHz 1200 1600 µA
ISD(VIN) VIN shutdown supply current VEN = 0 V, VVIN = 12 V 15 25 µA
VIN UVLO rising threshold VIN rising 3.9 4 4.1 V
VIN UVLO hysteresis 150 mV
ENABLE AND UVLO
VEN(rise) EN voltage rising threshold EN rising, enable switching 1.2 1.25 V
VEN(fall) EN voltage falling threshold EN falling, disable switching 1.05 1.1 V
VEN(hyst) EN voltage hysteresis 100 mV
EN pin sourcing current VEN = 1.1 V 0.4 1.5 µA
EN pin sourcing current VEN = 1.3 V 11.6 µA
INTERNAL LDO BP5
VBP5 Internal LDO BP5 output voltage VVIN = 12 V 4.5 V
BP5 dropout voltage VVIN – VBP5, VVIN = 3.8 V 350 mV
BP5 short-circuit current limit VVIN = 12 V 75 mA
REFERENCE VOLTAGE
VFB Feedback Voltage  TJ = –40°C to 150°C 497.5 500 502.5 mV
IFB(LKG) Input leakage current into FB pin VFB = 500 mV, non-switching, VVIN = 12 V, VEN = 0 V 1 nA
SWITCHING FREQUENCY AND OSCILLATOR
fSW Switching frequency RMODE = 24.3 kΩ 450 500 550 kHz
fSW Switching frequency RMODE = 17.4 kΩ 675 750 825 kHz
fSW Switching frequency RMODE = 11.8 kΩ 900 1000 1100 kHz
fSW Switching frequency RMODE = 8.06 kΩ 1350 1500 1650 kHz
fSW Switching frequency RMODE = 4.99 kΩ 1980 2200 2420 kHz
SYNCHRONIZATION
VIH(sync) High-level input voltage 1.8 V
VIL(sync) Low-level input voltage 0.8 V
SOFT-START
tSS1 Soft-start time RMODE = 1.78 kΩ 0.5 ms
tSS2 Soft-start time RMODE = 2.21 kΩ 1 ms
tSS3 Soft-start time RMODE = 2.74 kΩ 2 ms
tSS4 Soft-start time RMODE = 3.32 kΩ 4 ms
POWER STAGE
RDS(on)HS High-side MOSFET on-resistance TJ = 25°C, VVIN = 12 V, VBOOT-SW = 4.5 V 25 mΩ
RDS(on)LS1 Low-side MOSFET on-resistance: high current limit selected TJ = 25°C, VBP5 = 4.5 V,  RMODE = 1.78 kΩ 6.5 mΩ
RDS(on)LS2 Low-side MOSFET on-resistance: low current limit selected TJ = 25°C, VBP5 = 4.5 V,  RMODE = 22.1 kΩ 13.9 mΩ
VBOOT-SW(UV_r) BOOT-SW UVLO rising threshold VBOOT-SW rising 3.2 V
VBOOT-SW(UV_f) BOOT-SW UVLO falling threshold VBOOT-SW falling 2.8 V
TON(min) Minimum ON pulse width IOUT > ½ IL_PK-PK 30 37 ns
TOFF(min) Minimum OFF pulse width (1) 115 140 ns
CURRENT SENSE AND OVERCURRENT PROTECTION
IOC_HS_pk1 High-side peak current limit  RMODE = 1.78 kΩ 8.6 9 9.6 A
IOC_HS_pk2 High-side peak current limit RMODE = 22.1 kΩ 4.2 4.5 4.8 A
IOC_LS_src1 Low-side sourcing current limit  RMODE = 1.78 kΩ 6.4 7.3 8.1 A
IOC_LS_src2 Low-side sourcing current limit RMODE = 22.1 kΩ 3.65 4.2 4.65 A
IOC_LS_snk Low-side sinking current limit Current into SW pin 2.95 A
OUTPUT OVERVOLTAGE AND UNDERVOLTAGE PROTECTIONS
VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 120 % VREF
VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 80 % VREF
POWER GOOD
PGOOD threshold VFB rising (Fault) 113 116 119 % VREF
PGOOD threshold VFB falling (Good) 105 108 111 % VREF
PGOOD threshold VFB rising (Good) 89 92 95 % VREF
PGOOD threshold VFB falling (Fault) 81 84 87 % VREF
IPGOOD(LKG) Leakage current into PGOOD pin when open drain output is high VPGOOD = 4.7 V 5 µA
VPG(low) PGOOD low-level output voltage IPGOOD = 2 mA, VIN = 12 V 0.5 V
Min VIN for valid PGOOD output 0.9 1 V
HICCUP
Hiccup time before re-start 7*tSS ms
OUTPUT DISCHARGE
RDischg Output discharge resistance VVIN = 12 V, VSW = 0.5 V, power conversion disabled. 100 Ω
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold (1) Temperature rising 165 175 °C
THYST Thermal shutdown hysteresis (1) 12 °C
(1) Specified by design. Not production tested.