JAJSF46I March   2018  – March 2024 TPS62824 , TPS62824A , TPS62825 , TPS62825A , TPS62826 , TPS62826A , TPS62827 , TPS62827A

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pulse Width Modulation (PWM) Operation
      2. 7.3.2 Power Save Mode (PSM) Operation
      3. 7.3.3 Minimum Duty Cycle and 100% Mode Operation
      4. 7.3.4 Soft Start
      5. 7.3.5 Switch Current Limit and HICCUP Short-Circuit Protection
      6. 7.3.6 Undervoltage Lockout
      7. 7.3.7 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Enable, Disable, and Output Discharge
      2. 7.4.2 Power Good
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Setting The Output Voltage
        3. 8.2.2.3 Output Filter Design
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
        1. 8.4.2.1 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 サード・パーティ製品に関する免責事項
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 Power Good

The TPS6282x has a built-in power-good (PG) function. The PG pin goes high impedance when the output voltage has reached the nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low (see Table 7-1). The PG function is formed with a window comparator, which has an upper and lower voltage threshold. The PG pin is an open-drain output and is specified to sink up to 1mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5V.

The PG signal can be used for sequencing of multiple rails by connecting it to the EN pin of other converters. Leave the PG pin unconnected when not used. The PG rising edge has a 100µs blanking time and the PG falling edge has a deglitch delay of 20µs.

Table 7-1 PG Pin Logic
DEVICE CONDITIONSLOGIC STATUS
HIGH ZLOW
EnableEN = High, VFB ≥ 0.576V√
EN = High, VFB ≤ 0.552V√
EN = High, VFB ≤ 0.63V√
EN = High, VFB ≥ 0.66V√
ShutdownEN = Low√
Thermal ShutdownTJ > TJSD√
UVLO0.7V < VIN < VUVLO√
Power Supply RemovalVIN < 0.7V√