JAJSJL4B August   2020  – March 2021 TPS62912 , TPS62913

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Smart Config (S-CONF)
      2. 7.3.2  Device Enable (EN/SYNC)
      3. 7.3.3  Device Synchronization (EN/SYNC)
      4. 7.3.4  Spread Spectrum Modulation
      5. 7.3.5  Output Discharge
      6. 7.3.6  Undervoltage Lockout (UVLO)
      7. 7.3.7  Power-Good Output
      8. 7.3.8  Noise Reduction and Soft-Start Capacitor (NR/SS)
      9. 7.3.9  Current Limit and Short Circuit Protection
      10. 7.3.10 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fixed Frequency Pulse Width Modulation
      2. 7.4.2 Low Duty Cycle Operation
      3. 7.4.3 High Duty Cycle Operation (100% Duty Cycle)
      4. 7.4.4 Second Stage L-C Filter Compensation (Optional)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 External Component Selection
          1. 8.2.2.2.1 Switching Frequency Selection
          2. 8.2.2.2.2 Inductor Selection for the First L-C Filter
          3. 8.2.2.2.3 Output Capacitor Selection
          4. 8.2.2.2.4 Ferrite Bead Selection for Second L-C Filter
          5. 8.2.2.2.5 Input Capacitor Selection
          6. 8.2.2.2.6 Setting the Output Voltage
          7. 8.2.2.2.7 NR/SS Capacitor Selection
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Development Support
        1. 11.1.2.1 Custom Design With WEBENCH® Tools
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.2 Layout Example

GUID-20200811-CA0I-TLXH-FFR1-GFKVFWJMWP6C-low.gif Figure 10-1 Recommended Layout for Single L-C Filter
Note: The start winding of the inductor, as shown in the figures as a black dot, needs to be connected to the DC/DC converter switch pin, SW, to minimize capacitive coupling to the surrounding area.
Note: The red dot indicates where the feedback sense should be placed for the best DC regulation. For a single L-C configuration, it is placed near the VOUT capacitors. For a second L-C filter design, the feedback sense is placed near the load after the VOUT_FILT capacitors.
GUID-20200811-CA0I-M6QF-9SR5-MMZVH9T7B8BX-low.gif Figure 10-2 Recommended Layout for Design with Second L-C Filter
Note: The ferrite bead can be placed closer to the device as long as it is outside the keep out area, as shown in the figure as a red rectangular area. This placement avoids capacitive and electromagnetic coupling to the output of the ferrite bead. If the ferrite bead is placed in the keep out area, the filtering effect of the ferrite bead is greatly reduced. If the ferrite bead is routed through a via to the back side of the board, ensure adequate ground plane between the layers if the ferrite bead will be in this area.