JAJSFS2D November   2015  – May 2021 TPS65235

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Boost Converter
      2. 7.3.2  Linear Regulator and Current Limit
      3. 7.3.3  Boost Converter Current Limit
      4. 7.3.4  Charge Pump
      5. 7.3.5  Slew Rate Control
      6. 7.3.6  Short Circuit Protection, Hiccup and Overtemperature Protection
      7. 7.3.7  Tone Generation
      8. 7.3.8  Tone Detection
      9. 7.3.9  Disable and Enable
      10. 7.3.10 Component Selection
        1. 7.3.10.1 Boost Inductor
        2. 7.3.10.2 Capacitor Selection
        3. 7.3.10.3 Surge Components
        4. 7.3.10.4 Consideration for Boost Filtering and LNB Noise
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 TPS65235 I2C Update Sequence
    6. 7.6 Register Maps
      1. 7.6.1 Control Register 1 (address = 0x00H) [reset = 00010000]
      2. 7.6.2 Control Register 2 (address = 0x01H) [reset = 0000101]
      3. 7.6.3 Status Register (address = 0x02H) [reset = x0100000]
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application for DiSEqc1.x Support
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Typical Application for DiSEqc2.x Support
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Control Register 2 (address = 0x01H) [reset = 0000101]

Figure 7-13 Control Register 2
76543210
00001001
R/WR/WR/WR/WR/WR/WR/WR/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7 Control Register 2
BitFieldTypeResetDescription
7TONEAMPR/W01: 22 kHz tone amplitude is 750 mV (typ)
0: 22 kHz tone amplitude is 650 mV (typ)
6TIMERR/W01: Hiccup ON/OFF time set to 8 ms / 256 ms
0: Hiccup ON/OFF time set to 4 ms / 128 ms
5ISWR/W01: Boost switch peak current limit set to 5 x Iocp + 0.8 A
0: Boost switch peak current limit set to 3 x Iocp + 0.8 A
4FSETR/W01: 500 kHz switching frequency
0: 1 MHz switching frequency
3ENR/W11: LNB output voltage Enabled
0: LNB output disabled
2DOUTMODER/W01: Reserved, cannot set to "1"
0: DOUT is kept to low when DIN has the tone input
1TONE_AUTOR/W01: GDR (External bypass FET control) is automatically controlled by 22 kHz tones transmit
0: GDR (External bypass FET control) is controlled by TONE_TRANS
0TONE_TRANSR/W11: GDR output with VCP voltage. Bypass FET is ON for tone transmit from TPS65235
0: GDR output with VLNB voltage for tone receive. Bypass FET is OFF for tone receiving from satellite
Table 7-8 22-kHz Tone Receive Mode Selection
TONE_AUTO TONE_TRANS Bypass FET
0 0 OFF
0 1 ON
1 x Auto Detect

TPS65235 has full range of diagnostic flags for operation and debug. Processor can read the status register to check the error conditions. Once the error happens, the flags are changed, once the errors are gone, the flags are set back without I2C access.

If flags TSD and OCP are triggered, FAULT pin will be pulled low, so FAULT pin can be the interrupt signal to processor. Once TSD and OCP are set to “1”, the FAULT pin logic is latched to low, processor need to read this status register in order to release the fault conditions.