JAJSD95A July   2016  – May 2017 TPS65381A-Q1

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 代表的なアプリケーションの図
  2. 2 改訂履歴
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
    7. 4.7 Switching Characteristics
    8. 4.8 Typical Characteristics
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1 VDD6 Buck Switch-Mode Power Supply
      2. 5.3.2 VDD5 Linear Regulator
      3. 5.3.3 VDD3/5 Linear Regulator
      4. 5.3.4 VDD1 Linear Regulator
      5. 5.3.5 VSOUT1 Linear Regulator
      6. 5.3.6 Charge Pump
      7. 5.3.7 Wake-Up
      8. 5.3.8 Reset Extension
    4. 5.4 Device Functional Modes
      1. 5.4.1  Power-Up and Power-Down Behavior
      2. 5.4.2  Safety Functions and Diagnostics Overview
      3. 5.4.3  Voltage Monitor (VMON)
      4. 5.4.4  TPS65381A-Q1 Internal Error Signals
      5. 5.4.5  Loss-of-Clock Monitor (LCMON)
      6. 5.4.6  Analog Built-In Self-Test (ABIST)
      7. 5.4.7  Logic Built-In Self-Test (LBIST)
      8. 5.4.8  Junction Temperature Monitoring and Current Limiting
      9. 5.4.9  Diagnostic MUX and Diagnostic Output Pin (DIAG_OUT)
        1. 5.4.9.1 Analog MUX (AMUX)
        2. 5.4.9.2 Digital MUX (DMUX)
        3. 5.4.9.3 Diagnostic MUX Output State (by MUX_OUT bit)
        4. 5.4.9.4 MUX Interconnect Check
      10. 5.4.10 Watchdog Timer (WD)
      11. 5.4.11 Watchdog Fail Counter, Status, and Fail Event
      12. 5.4.12 Watchdog Sequence
      13. 5.4.13 MCU to Watchdog Synchronization
      14. 5.4.14 Trigger Mode (Default Mode)
      15. 5.4.15 Q&A Mode
        1. 5.4.15.1 Watchdog Q&A Related Definitions
        2. 5.4.15.2 Watchdog Sequence in Q&A Mode
        3. 5.4.15.3 Question (Token) Generation
        4. 5.4.15.4 Answer Comparison and Reference Answer
          1. 5.4.15.4.1 Sequence of the 2-bit Watchdog Answer Counter
        5. 5.4.15.5 Watchdog Q&A Mode Sequence Events and WD_STATUS Register Updates
      16. 5.4.16 MCU Error Signal Monitor (MCU ESM)
        1. 5.4.16.1 TMS570 Mode
        2. 5.4.16.2 PWM Mode
      17. 5.4.17 Device Configuration Register Protection
      18. 5.4.18 Enable and Reset Driver Circuit
      19. 5.4.19 Device Operating States
      20. 5.4.20 STANDBY State
      21. 5.4.21 RESET State
      22. 5.4.22 DIAGNOSTIC State
      23. 5.4.23 ACTIVE State
      24. 5.4.24 SAFE State
      25. 5.4.25 State Transition Priorities
      26. 5.4.26 Power on Reset (NPOR)
    5. 5.5 Register Maps
      1. 5.5.1 Serial Peripheral Interface (SPI)
        1. 5.5.1.1 SPI Command Transfer Phase
        2. 5.5.1.2 SPI Data-Transfer Phase
        3. 5.5.1.3 Device Status Flag Byte Response
        4. 5.5.1.4 Device SPI Data Response
        5. 5.5.1.5 SPI Frame Overview
      2. 5.5.2 SPI Register Write Access Lock (SW_LOCK command)
      3. 5.5.3 SPI Registers (SPI Mapped Response)
        1. 5.5.3.1 Device Revision and ID
          1. 5.5.3.1.1 DEV_REV Register
          2. 5.5.3.1.2 DEV_ID Register
        2. 5.5.3.2 Device Status
          1. 5.5.3.2.1 DEV_STAT Register
        3. 5.5.3.3 Device Configuration
          1. 5.5.3.3.1 DEV_CFG1 Register
          2. 5.5.3.3.2 DEV_CFG2 Register
      4. 5.5.4 Device Safety Status and Control Registers
        1. 5.5.4.1  VMON_STAT_1 Register
        2. 5.5.4.2  VMON_STAT_2 Register
        3. 5.5.4.3  SAFETY_STAT_1 Register
        4. 5.5.4.4  SAFETY_STAT_2 Register
        5. 5.5.4.5  SAFETY_STAT_3 Register
        6. 5.5.4.6  SAFETY_STAT_4 Register
        7. 5.5.4.7  SAFETY_STAT_5 Register
        8. 5.5.4.8  SAFETY_ERR_CFG Register
        9. 5.5.4.9  SAFETY_BIST_CTRL Register
        10. 5.5.4.10 SAFETY_CHECK_CTRL Register
        11. 5.5.4.11 SAFETY_FUNC_CFG Register
        12. 5.5.4.12 SAFETY_ERR_STAT Register
        13. 5.5.4.13 SAFETY_ERR_PWM_H Register
        14. 5.5.4.14 SAFETY_ERR_PWM_L Register
        15. 5.5.4.15 SAFETY_PWD_THR_CFG Register
        16. 5.5.4.16 SAFETY_CFG_CRC Register
        17. 5.5.4.17 Diagnostics
          1. 5.5.4.17.1 DIAG_CFG_CTRL Register
          2. 5.5.4.17.2 DIAG_MUX_SEL Register
      5. 5.5.5 Watchdog Timer
        1. 5.5.5.1 WD_TOKEN_FDBK Register
        2. 5.5.5.2 WD_WIN1_CFG Register
        3. 5.5.5.3 WD_WIN2_CFG Register
        4. 5.5.5.4 WD_TOKEN_VALUE Register
        5. 5.5.5.5 WD_STATUS Register
        6. 5.5.5.6 WD_ANSWER Register
      6. 5.5.6 Sensor Supply
        1. 5.5.6.1 SENS_CTRL Register
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 VDD6 Preregulator
        2. 6.2.2.2 VDD1 Linear Controller
        3. 6.2.2.3 VSOUT1 Tracking Linear Regulator, Configured to Track VDD5
        4. 6.2.2.4 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 6-V Output Tracking VDD3/5 In 3.3-V Mode
        5. 6.2.2.5 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured for 9-V Output Tracking to 5-V Input from VDD5
        6. 6.2.2.6 Alternative Use for VSOUT1 Tracking Linear Regulator, Configured in Non-tracking Mode Providing a 4.5-V Output
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
      1. 8.1.1 VDD6 Buck Preregulator
      2. 8.1.2 VDD1 Linear Regulator Controller
      3. 8.1.3 VDD5 and VDD3/5 Linear Regulators
      4. 8.1.4 VSOUT1 Tracking Linear Regulator
      5. 8.1.5 Charge Pump
      6. 8.1.6 Other Considerations
    2. 8.2 Layout Example
    3. 8.3 Power Dissipation and Thermal Considerations
  9. 9 デバイスおよびドキュメントのサポート
    1. 9.1 ドキュメントのサポート
      1. 9.1.1 関連資料
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 Community Resources
    4. 9.4 商標
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 Glossary
  10. 10メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

3 Pin Configuration and Functions

The pin configuration drawing in this section is not to scale. For package dimensions, see the mechanical data in Section 10.

DAP Package
32-Pin HTSSOP With PowerPAD™
Top View

TPS65381A-Q1 32_DAP_sop_pin_diagram.gif

Pin Functions

PIN TYPE DESCRIPTION
NO. NAME
1 VBAT_SAFING PWR Battery (supply) input for monitoring (VMON) and BG2 functions (must be reverse protected), should be connected to VBATP
2 VCP PWR Charge-pump output voltage
3 CP1 PWR Charge-pump external capacitor, high-voltage side
4 CP2 PWR Charge-pump external capacitor, low-voltage side
5 PGND GND Ground (power)
6 NRES O Cold reset output signal for the microcontroller (MCU) (active-low, internal pullup, open drain output)
7 DIAG_OUT O Diagnostic output pin for diagnostic MUX. Internal analog (AMUX) and digital (DMUX) signal connection to MCU ADC and digital IO
8 NCS I SPI chip select (active-low, internal pullup)
9 SDI I SPI serial data IN (internal pulldown)
10 SDO O SPI serial data OUT
11 SCLK I SPI clock (internal pull down)
12 RSTEXT I Configuration pin to set reset extension time through a resistor to GND
13 ERROR/WDI I Error input signal from the MCU while using the MCU ESM (with the watchdog in Q&A Mode), trigger input for the watchdog in trigger mode (MCU ESM not used). This pin is edge triggered.
14 CANWU I Wake-up input from CAN transceiver, other transceiver or other source. Wake-up request latched with CANWU_L. (internal pulldown)
15 VSFB1 I Feedback input reference for sensor supply regulator (VSOUT1)
16 VSIN PWR Input supply voltage for the sensor-supply regulator (VSOUT1)
17 VSOUT1 PWR Output voltage for the VSOUT1 sensor-supply regulator
18 VTRACK1 I Tracking input reference for sensor-supply regulator (VSOUT1) (internal pulldown)
19 GND GND Ground (analog)
23 GND GND Ground (analog)
20 VDD5 PWR VDD5 regulator output voltage
21 VDD3/5 PWR VDD3/5 regulator output voltage
22 VDDIO PWR I/O supply input for pins to and from the MCU
24 VDD1_SENSE I Reference input for VDD1 regulator (feedback) and input for UV/OV monitoring of VDD1 regulator
25 PGND GND Ground (power)
26 VDD1_G O Gate drive of external FET for VDD1 regulator
27 VDD6 PWR VDD6 switch mode regulator feedback input and supply input for integrated VDD5 and VDD3/5 regulators
28 SDN6 PWR Switching node for VDD6 switch mode regulator
29 VBATP PWR Battery (supply) voltage (must be reverse protected), main power supply input for device
30 IGN I Wake-up input from ignition (key) or other source (internal pulldown)
31 SEL_VDD3/5 I Input selects voltage level for VDD3/5 regulator (SEL_VDD3/5 pin open: 3.3-V regulation from VDD3/5; SEL_VDD3/5 pin to GND: 5-V regulation from VDD3/5)
32 ENDRV O Enable output signal for peripherals (for example, motor-driver IC), safing path output (internal pullup, open drain output)
— Thermal pad — Place thermal vias to large ground plane and connect to GND and PGND pins.