JAJSEF6L August   2013  – February 2019 TPS659038-Q1 , TPS659039-Q1

PRODUCTION DATA.  

  1. 1 デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 2 改訂履歴
  3. 3 Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions
      1.      Pin Functions
    2. 4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
    3. 4.3 Signal Descriptions
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Latch Up Rating
    6. 5.6  Electrical Characteristics: LDO Regulator
    7. 5.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 5.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 5.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 5.11 Electrical Characteristics: DC-DC Clock Sync
    12. 5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 5.14 Electrical Characteristics: System Control Thresholds
    15. 5.15 Electrical Characteristics: Current Consumption
    16. 5.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 5.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
    19. 5.19 I2C Interface Timing Requirements
    20. 5.20 SPI Timing Requirements
    21. 5.21 Typical Characteristics
  6. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1  Power Management
      2. 6.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 6.3.2.1 Step-Down Regulators
          1. 6.3.2.1.1 Sync Clock Functionality
          2. 6.3.2.1.2 Output Voltage and Mode Selection
          3. 6.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 6.3.2.1.4 POWERGOOD
          5. 6.3.2.1.5 DVS-Capable Regulators
          6. 6.3.2.1.6 Non DVS-Capable Regulators
          7. 6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 6.3.2.2 LDOs – Low Dropout Regulators
          1. 6.3.2.2.1 LDOVANA
          2. 6.3.2.2.2 LDOVRTC
          3. 6.3.2.2.3 LDO Bypass (LDO9)
          4. 6.3.2.2.4 LDOUSB
          5. 6.3.2.2.5 Other LDOs
      3. 6.3.3  Long-Press Key Detection
      4. 6.3.4  RTC
        1. 6.3.4.1 General Description
        2. 6.3.4.2 Time Calendar Registers
          1. 6.3.4.2.1 TC Registers Read Access
          2. 6.3.4.2.2 TC Registers Write Access
        3. 6.3.4.3 RTC Alarm
        4. 6.3.4.4 RTC Interrupts
        5. 6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 6.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 6.3.5.1 Asynchronous Conversion Request (SW)
        2. 6.3.5.2 Periodic Conversion Request (AUTO)
        3. 6.3.5.3 Calibration
      6. 6.3.6  General-Purpose I/Os (GPIO Terminals)
        1. 6.3.6.1 REGEN Output
      7. 6.3.7  Thermal Monitoring
        1. 6.3.7.1 Hot-Die Function (HD)
        2. 6.3.7.2 Thermal Shutdown (TS)
        3. 6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 6.3.8  Interrupts
      9. 6.3.9  Control Interfaces
        1. 6.3.9.1 I2C Interfaces
          1. 6.3.9.1.1 I2C Implementation
          2. 6.3.9.1.2 F/S Mode Protocol
          3. 6.3.9.1.3 HS Mode Protocol
        2. 6.3.9.2 SPI Interface
          1. 6.3.9.2.1 SPI Modes
          2. 6.3.9.2.2 SPI Protocol
      10. 6.3.10 Device Identification
    4. 6.4 Device Functional Modes
      1. 6.4.1  Embedded Power Controller
      2. 6.4.2  State Transition Requests
        1. 6.4.2.1 ON Requests
        2. 6.4.2.2 OFF Requests
        3. 6.4.2.3 SLEEP and WAKE Requests
      3. 6.4.3  Power Sequences
      4. 6.4.4  Start Up Timing and RESET_OUT Generation
      5. 6.4.5  Power On Acknowledge
        1. 6.4.5.1 POWERHOLD Mode
        2. 6.4.5.2 AUTODEVON Mode
      6. 6.4.6  BOOT Configuration
        1. 6.4.6.1 Boot Terminal Selection
      7. 6.4.7  Reset Levels
      8. 6.4.8  Warm Reset
      9. 6.4.9  RESET_IN
      10. 6.4.10 Watchdog Timer (WDT)
      11. 6.4.11 System Voltage Monitoring
        1. 6.4.11.1 Generating a POR
  7. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Recommended External Components
        2. 7.2.2.2  SMPS Input Capacitors
        3. 7.2.2.3  SMPS Output Capacitors
        4. 7.2.2.4  SMPS Inductors
        5. 7.2.2.5  LDO Input Capacitors
        6. 7.2.2.6  LDO Output Capacitors
        7. 7.2.2.7  VCC1
          1. 7.2.2.7.1 Meeting the Power Down Sequence
          2. 7.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 7.2.2.8  VIO_IN
        9. 7.2.2.9  16-MHz Crystal
        10. 7.2.2.10 GPADC
      3. 7.2.3 Application Curves
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 デバイスの項目表記
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 関連リンク
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 Community Resources
    6. 10.6 商標
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 パッケージ・マテリアル情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ZWS|169
サーマルパッド・メカニカル・データ
発注情報

2 改訂履歴

Changes from K Revision (January 2018) to L Revision

  • ESD 分類を C4B から C3 に変更Go
  • Updated the LDOVRTC_OUT pulldown resistor recommendation to only include applicable silicon revisions. Go
  • Changed ESD Ratings for charge device model on 6 pins Go
  • Clarified that LDO1 and LDO2 input pins are not included in this minimum recommended operating voltage. See Electrical Characteristics: LDO Regulators for more information. Go
  • Changed minimum recommended operating condition of OSC16MIN from 0V to -0.7V Go
  • Added LDO and SMPS output capacitance footnote Go
  • Changed VSYS_LO hysteresis from 95mV to 75mVGo
  • Updated Caution statement to only include applicable silicon revisions. Go
  • Changed discharge resistance to match electrical characteristics table Go
  • Added information about shutdown timing during short circuit detection Go
  • Updated POWERGOOD description to clarify multi-phase operation. Go
  • Updated LDOVRTC note to only include applicable silicon revisions.Go
  • Added details on identifying device version.Go
  • Added typical debounce time from POWERHOLD to the enable of the first rail in the power sequence. Go
  • Added VSYS_LO note for applicable silicon revisions. Go
  • Updated POR requirements to only include applicable silicon revisions. Go
  • SMPS and LDO output capacitance specification further explained Go
  • Added design considerations for VCC1 capacitance to support loss of powerGo
  • Corrected 9-Vpp with 7V absolute maximum specification in the Layout Guidelines sectionGo
  • Updated requirements relating to measurement of high-side and low-side FETs in the Layout Guidelines sectionGo
  • Updated images and description on differential measurements across high-side and low-side FETs Go

Changes from J Revision (March 2017) to K Revision

  • Removed pullup and pulldown from BOOT0 pin descriptionGo
  • Deleted the nominal Tstg value (27°C) from the Absolute Maximum Ratings tableGo
  • Deleted the voltage mode to the I/O digital supply voltage, VIO_IN parameter from the Recommended Operating Conditions tableGo
  • Deleted the voltage on the VCC1 GPADC pins (TBC) parameter from the Recommended Operating Conditions tableGo
  • Added 2-A mode for SMPS6 in the test conditions for high-side and low-side MOSFET forward current limit and low-side MOSFET negative current limit in the Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9) tableGo
  • Added the number of active SMPS phases (K) to the equation for the temperature compensated result in the Current Monitoring and Short Circuit Detection sectionGo
  • Added additional description of SMPS short detection and recovery behaviorGo
  • Added equation to convert GPADC code to internal die temperatureGo
  • Added description of VIO power-up timing, and updated start up timing diagramGo
  • Added additional description of VSYS_LO functionalityGo
  • Added link to application note about POR generationGo

Changes from I Revision (June 2016) to J Revision

  • データシートの初回一般公開Go
  • Added recommendation for external pulldown resistor on the LDOVRTC_OUT pin in the Pin Functions tableGo
  • Changed the description of the LDOVRTC when in the BACKUP and OFF states and added a note in the LDOVRTC section Go
  • Added the note and pulldown equations to the System Voltage Monitoring sectionGo

Changes from H Revision (October 2015) to I Revision

  • Changed the typical value for the Channel 11 SMPS output current measurement gain factor parameter in the 12-Bit Sigma-Delta ADC tableGo
  • Changed the typical value for the channel 11 SMPS output current measurement current offset parameter in the 12-Bit Sigma-Delta ADC tableGo
  • Updated part numbers and settings for released devices in the Design Parameters tableGo

Changes from G Revision (October 2015) to H Revision

  • Added DC accuracy spec for LDO3 and LDO4 when IO = 300 mA, which is the new IOmax from the previous revisionGo
  • Added VDROPOUT spec for LDO3 and LDO4 when IO = 300 mA, which is the new IOmax from the previous revisionGo
  • Added DC Load Regulation spec for LDO3 and LDO4 when IO = 300 mA, which is the new IOmax from the previous revisionGo
  • Updated PSRR spec for LDO3 and LDO4 when IO = 300 mA, which is the new IOmax from the previous revision Go
  • Added DC Load Transient spec for LDO3 and LDO4 when IO = 300 mA, which is the new IOmax from the previous revision Go
  • Updated the current capability of LDO3 and LDO4 from 200 mA to 300 mA throughout the specification Go

Changes from F Revision (February 2015) to G Revision

  • Updated the functional block diagram by removing the external connections and combining both 38/39 devices in one diagram.Go
  • Added caution statement for operating the GPADC in SW mode. Go
  • Updated the component numbering in the Typical Applications Diagrams to align with EVM schematics and Table 7-2Go
  • Added description of OSC16M_CFG OTP bit, and the required setting of this bit in relation to the presence of a 16-MHz crystal for proper device function.Go

Changes from E Revision (December 2014) to F Revision

  • Changed the DVS-Capable Regulators section; the slew rate of the output voltage is fixed at 2.5 mV/µsGo
  • Updated the Design Requirements section Go
  • Changed the REFERENCE COMPONENT numbers in the Recommended External Components for Automotive Usage table Go
  • Deleted the Recommended External Components for Commercial Usage table from the Typical Application section Go
  • Changed the body size for CX8045GB16384H0HEQZ1 in the Recommended External Components for Automotive Usage tableGo
  • Deleted the GPADC EXTERNAL COMPONENTS from the Recommended External Components for Automotive Usage tableGo

Changes from D Revision (October 2014) to E Revision

  • Added caution statement to the Specifications section Go
  • Added caution statement to the Specifications section Go

Changes from C Revision (June 2014) to D Revision

  • Deleted データシートから輸出管理通知をGo
  • Removed all notions of (3.6V tolerance) from VRTC digital pins without fail-safe featureGo
  • Changed Replaced LDOVRTCmax + 0.3 notion with actual value of 2.15 under the ABS Max Rating table for VRTC digital input pinsGo
  • Changed Replaced LDOVRTCmax notion with actual value of 1.85 under the ROC table for OSC16MIN and VRTC digital input pinsGo
  • Updated typical IQ(on) value of LDOUSB-IN1 from 30µA to 45µA in accordance with characterization data Go
  • Added Caution clause to describe the scenario which may cause unexpected shutdown of the PLL, and the actions to recover from such fault condition.Go
  • Added comments for the ideal SMPS voltage-spike measurement condition under Layout Guidance section. Go

Changes from B Revision (June 2014) to C Revision

  • Updated Latch Up Current Class specification format and separated LDOVANA_OUT pin specification from all other pinsGo
  • Updated typical value of high-side FET rDS(on) from 50mΩ to 115mΩ for all multi-phase SMPSs Go
  • Updated typical value of low-side FET rDS(on) from 39mΩ to 30mΩ for all multi-phase SMPSs Go
  • Updated typical value of High-side FET rDS(on) from 50mΩ to 115mΩ for all single-phase SMPSs except SMPS 8 & 9 Go
  • Updated typical value of high-side FET rDS(on) from 110mΩ to 180mΩ for SMPS8 & 9 Go
  • Updated typical value of low-side FET rDS(on) from 39mΩ to 30mΩ for all single-phase SMPSs except SMPS 8 & 9 Go
  • Updated the typical value of CLK32KGO output buffer rise and fall time based on characterization data. Go
  • Updated the min and max value of CLK32KGO1V8 output buffer rise and fall time based on simulation data. Go
  • Added comments on limitation of Vout/Vin ratio and Vin monitor and shut down mechanism when a SMPS converter is in ECO mode.Go

Changes from A Revision (May 2014) to B Revision

  • Corrected the default state of the NSLEEP pin to PPU under Pin Function tableGo
  • Corrected the voltage range for the GPADC_IN0 and GPADC_IN1 pins under the Recommended Operating Conditions tableGo
  • Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in multi-phase configuration Go
  • Reduced minimum output inductance to -30% of the recommended value of 1µH for SMPSs in single-phase configuration Go
  • Added device Current Consumption specification for Sleep Mode when VSYS = 5.25VGo
  • Added paragraph with regards to the importance of VSYS being the first supply available to the device. Go
  • Added approximate power rail shut down time from a short detectionGo
  • Added approximate wait time for the device to reach OFF state from No Supply state.Go
  • Added a paragraph under the Application Information section to emphasize the importance of operating the device under ROC, and encourage customers to consider thermal management, power sequencing and layout strategy to maximize device performance.Go

Changes from * Revision (April 2014) to A Revision

  • Added option to float the VPROG pin when it is configured as an input pin Go
  • Updated Output Type of I2C2_SDA_SDO pin to specify Push-pull type when the pin is configured in SPI modeGo
  • Corrected the minimum voltage level for all SMPS-related input pins to match VSYS minimum input level in Recommended Operating Conditions Go
  • Moved Latch Up Current Classification table out of the Handling Ratings tableGo
  • Corrected editing error which added an invalid Ripple spec for LDO1 & LDO2Go
  • Updated the maximum specification of device Current Consumption in OFF Mode from 30 µA to 45 µA Go
  • Updated the definition and test condition of the device Current Consumption in SLEEP mode from having only SMPS6 and SMPS8 enabled to having only LDO2 and LDO9 enabled. Also updated the typical and maximum specifications to associate with the new definition.Go
  • Added the specific description that SDO line defaults to high impedance when the pin is configured as SPI mode. Go
  • Corrected the recommended part number for the Crystal decoupling caps in automotive use caseGo