JAJSEF6L August   2013  – February 2019 TPS659038-Q1 , TPS659039-Q1

PRODUCTION DATA.  

  1. デバイスの概要
    1. 1.1 特長
    2. 1.2 アプリケーション
    3. 1.3 概要
    4. 1.4 ブロック概略図
  2. 改訂履歴
  3. Device Comparison
  4. Pin Configuration and Functions
    1. 4.1 Pin Functions
      1.      Pin Functions
    2. 4.2 Device Ball Mapping – 13 × 13 nFBGA, 169 Balls, 0,8-mm Pitch
    3. 4.3 Signal Descriptions
  5. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: Latch Up Rating
    6. 5.6  Electrical Characteristics: LDO Regulator
    7. 5.7  Electrical Characteristics: Dual-Phase (SMPS12 and SMPS45) and Triple-Phase (SMPS123 and SMPS457) Regulators
    8. 5.8  Electrical Characteristics: Stand-Alone Regulators (SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9)
    9. 5.9  Electrical Characteristics: Reference Generator (Bandgap)
    10. 5.10 Electrical Characteristics: 16-MHz Crystal Oscillator, 32-kHz RC Oscillator, and Output Buffers
    11. 5.11 Electrical Characteristics: DC-DC Clock Sync
    12. 5.12 Electrical Characteristics: 12-Bit Sigma-Delta ADC
    13. 5.13 Electrical Characteristics: Thermal Monitoring and Shutdown
    14. 5.14 Electrical Characteristics: System Control Thresholds
    15. 5.15 Electrical Characteristics: Current Consumption
    16. 5.16 Electrical Characteristics: Digital Input Signal Parameters
    17. 5.17 Electrical Characteristics: Digital Output Signal Parameters
    18. 5.18 Electrical Characteristics: I/O Pullup and Pulldown Resistance
    19. 5.19 I2C Interface Timing Requirements
    20. 5.20 SPI Timing Requirements
    21. 5.21 Typical Characteristics
  6. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1  Power Management
      2. 6.3.2  Power Resources (Step-Down and Step-Up SMPS Regulators, LDOs)
        1. 6.3.2.1 Step-Down Regulators
          1. 6.3.2.1.1 Sync Clock Functionality
          2. 6.3.2.1.2 Output Voltage and Mode Selection
          3. 6.3.2.1.3 Current Monitoring and Short Circuit Detection
          4. 6.3.2.1.4 POWERGOOD
          5. 6.3.2.1.5 DVS-Capable Regulators
          6. 6.3.2.1.6 Non DVS-Capable Regulators
          7. 6.3.2.1.7 Step-Down Converters SMPS12 and SMPS123
            1.         a. Dual-Phase SMPS and Stand-Alone SMPS
            2.         b. Triple Phase SMPS
          8. 6.3.2.1.8 Step-Down Converter SMPS45 and SMPS457
          9. 6.3.2.1.9 Step-Down Converters SMPS3, SMPS6, SMPS7, SMPS8, and SMPS9
        2. 6.3.2.2 LDOs – Low Dropout Regulators
          1. 6.3.2.2.1 LDOVANA
          2. 6.3.2.2.2 LDOVRTC
          3. 6.3.2.2.3 LDO Bypass (LDO9)
          4. 6.3.2.2.4 LDOUSB
          5. 6.3.2.2.5 Other LDOs
      3. 6.3.3  Long-Press Key Detection
      4. 6.3.4  RTC
        1. 6.3.4.1 General Description
        2. 6.3.4.2 Time Calendar Registers
          1. 6.3.4.2.1 TC Registers Read Access
          2. 6.3.4.2.2 TC Registers Write Access
        3. 6.3.4.3 RTC Alarm
        4. 6.3.4.4 RTC Interrupts
        5. 6.3.4.5 RTC 32-kHz Oscillator Drift Compensation
      5. 6.3.5  GPADC – 12-Bit Sigma-Delta ADC
        1. 6.3.5.1 Asynchronous Conversion Request (SW)
        2. 6.3.5.2 Periodic Conversion Request (AUTO)
        3. 6.3.5.3 Calibration
      6. 6.3.6  General-Purpose I/Os (GPIO Terminals)
        1. 6.3.6.1 REGEN Output
      7. 6.3.7  Thermal Monitoring
        1. 6.3.7.1 Hot-Die Function (HD)
        2. 6.3.7.2 Thermal Shutdown (TS)
        3. 6.3.7.3 Temperature Monitoring With External NTC Resistor or Diode
      8. 6.3.8  Interrupts
      9. 6.3.9  Control Interfaces
        1. 6.3.9.1 I2C Interfaces
          1. 6.3.9.1.1 I2C Implementation
          2. 6.3.9.1.2 F/S Mode Protocol
          3. 6.3.9.1.3 HS Mode Protocol
        2. 6.3.9.2 SPI Interface
          1. 6.3.9.2.1 SPI Modes
          2. 6.3.9.2.2 SPI Protocol
      10. 6.3.10 Device Identification
    4. 6.4 Device Functional Modes
      1. 6.4.1  Embedded Power Controller
      2. 6.4.2  State Transition Requests
        1. 6.4.2.1 ON Requests
        2. 6.4.2.2 OFF Requests
        3. 6.4.2.3 SLEEP and WAKE Requests
      3. 6.4.3  Power Sequences
      4. 6.4.4  Start Up Timing and RESET_OUT Generation
      5. 6.4.5  Power On Acknowledge
        1. 6.4.5.1 POWERHOLD Mode
        2. 6.4.5.2 AUTODEVON Mode
      6. 6.4.6  BOOT Configuration
        1. 6.4.6.1 Boot Terminal Selection
      7. 6.4.7  Reset Levels
      8. 6.4.8  Warm Reset
      9. 6.4.9  RESET_IN
      10. 6.4.10 Watchdog Timer (WDT)
      11. 6.4.11 System Voltage Monitoring
        1. 6.4.11.1 Generating a POR
  7. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Recommended External Components
        2. 7.2.2.2  SMPS Input Capacitors
        3. 7.2.2.3  SMPS Output Capacitors
        4. 7.2.2.4  SMPS Inductors
        5. 7.2.2.5  LDO Input Capacitors
        6. 7.2.2.6  LDO Output Capacitors
        7. 7.2.2.7  VCC1
          1. 7.2.2.7.1 Meeting the Power Down Sequence
          2. 7.2.2.7.2 Maintaining Sufficient Input Voltage
        8. 7.2.2.8  VIO_IN
        9. 7.2.2.9  16-MHz Crystal
        10. 7.2.2.10 GPADC
      3. 7.2.3 Application Curves
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 デバイスの項目表記
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 関連リンク
    4. 10.4 ドキュメントの更新通知を受け取る方法
    5. 10.5 Community Resources
    6. 10.6 商標
    7. 10.7 静電気放電に関する注意事項
    8. 10.8 Glossary
  11. 11メカニカル、パッケージ、および注文情報
    1. 11.1 パッケージ・マテリアル情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ZWS|169
サーマルパッド・メカニカル・データ
発注情報

Interrupts

Table 6-6 lists the TPS65903x-Q1 interrupts.

These interrupts are split into four register groups (INT1, INT2, INT3, INT4) and each group has three associated control registers:

  • INTx_STATUS: Reflects which interrupt source has triggered an interrupt event
  • INTx_MASK: Used to mask any source of interrupt, to avoid generating an interrupt on a specified source
  • INTx_LINE_STATE: Reflects the real-time state of each line associated to each source of interrupt

The INT4 register group has two additional registers, INT4_EDGE_DETECT1 and
INT4_EDGE_DETECT2, to independently configure rising and falling edge detection.

All interrupts are logically combined on a single output line INT (default active low). This line is used as an external interrupt line to warn the host processor of any interrupt event that has occurred within the device. The host processor has to read the interrupt status registers (INTx_STATUS) through the control interface (I2C or SPI) to identify the interrupt source(s). Any interrupt source can be masked by programming the corresponding mask register (INTx_MASK). When an interrupt is masked, its associated event detection mechanism is disabled. Therefore the corresponding STATUS bit is not updated and the INT line is not triggered if the masked event occurs. Any event happening while its corresponding interrupt is masked is lost. If an interrupt is masked after it has been triggered (event has occurred and has not yet been cleared), then the STATUS bit reflects the event until it is cleared and it does not trigger again if a new event occurs (because it is now masked).

Because some interrupts are sources of ON requests (see Table 6-6), source masking can be used to mask a specific device switch-on event. Because an active interrupt line INT is treated as an ON request, any interrupt not masked must be cleared to allow the execution of a SLEEP sequence of the device when requested.

The INT line polarity and interrupts clearing method can be configured using the INT_CTRL register.

An INT line event can be provided to the host in either SLEEP or ACTIVE mode, depending on the setting of the OSC_THERM_CTRL.INT_MASK_IN_SLEEP bit.

When a new interrupt occurs while the interrupt line INT is still active (not all interrupts have been cleared), then:

  • If the new interrupt source is the same as the one that has already triggered the INT line, it can be discarded or stored as a pending interrupt depending on the setting of the INT_CTRL.INT_PENDING bit.
    • When the INT_CTRL.INT_PENDING bit is active (default), then any new interrupt event occurring on the same source (while the INT line is still active) is stored as a pending interrupt. Because only one level of pending interrupt can be stored for a given source, when several events (more than two) occur on the same source, only the last one is stored. While an interrupt is pending, two accesses are needed (either read or write) to clear the STATUS bit: one access for the actual interrupt and another for the pending interrupt. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations. Example for clear-on-read: when INT signal is active, read all four INTx_STATUS registers in sequence to collect status of all potential interrupt sources. Read access clears the full register for an active or actual interrupt. If the INT line is still active, repeat read sequence to check and clear pending interrupts.
    • When the INT_CTRL.INT_PENDING bit is inactive, then any new interrupt event occurring on the same source (while the INT line is still active) is discarded. Note: two consecutive read or write operations to the same register clear only one interrupt. Another register must be accessed between the two read or write clear operations.
  • If the new interrupt source is different from the one that already triggered the INT line, then it is stored immediately into its corresponding STATUS bit.

To clear the interrupt line, all status registers must be cleared. The clearing of all status registers is achieved by using a clear-on-read or a clear-on-write method. The clearing method is selectable though the INT_CTRL.INT_CLEAR bit. Once set, the clearing method applies to all bits for all interrupts.

  • Clear-on-read
    • Read access to a single status register clears all the bits for only this specific register (8 bits). Therefore, clearing all interrupts requests to read the four status registers. If the INT line is still active when the four read accesses complete, then another interrupt event has occurred during the read process; therefore the read sequence must be repeated.
  • Clear-on-write
    • This method is bit-based; setting a specific bit to 1 clears only the written bit. Therefore, to clear a complete status register, 0xFF must be written. Clearing all interrupts requests to write 0xFF into the four status registers. If the INT line is still active when the four write accesses are complete, then another interrupt event has occurred during the write process; therefore the write sequence must be repeated.

Table 6-6 Interrupt Sources

INTERRUPT ASSOCIATED EVENT EDGES DETECTION ON REQUEST REG. GROUP REG. BIT DESCRIPTION
VSYS_MON Internal event Rising and falling Never INT1 6 System voltage monitoring interrupt: Triggered when system voltage has crossed the configured threshold in VSYS_MON register.
HOTDIE Internal event Rising and falling Never 5 Hot-die temperature interrupt: The embedded thermal monitoring module has detected a die temperature above the hot-die detection threshold. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state.
PWRDOWN PWRDOWN (terminal) Rising and falling Never 4 Power-down interrupt: Triggered when the event is detected on the PWRDOWN terminal.
RPWRON RPWRON (terminal) Falling Always
(INT mask don't care)
3 Remote power-on interrupt: Triggered when a signal change is detected. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state.
LONG_PRESS_KEY PWRON (terminal) Falling Never 2 Power-on long key-press interrupt. Triggered when PWRON is low during more than the long-press delay LONG_PRESS_KEY.LPK_TIME.
PWRON PWRON (terminal) Falling Always
(INT mask don't care)
1 Power-on interrupt: Triggered when PWRON button is pressed (low) while the device is on. Interrupt is generated in ACTIVE and SLEEP state, not in OFF state.
SHORT Internal event Rising Yes
(if INT not masked)
INT2 6 Short interrupt: Triggered when at least one of the power resources (SMPS or LDO) has its output shorted.
RESET_IN RESET_IN (terminal) Rising Never 4 RESET_IN interrupt: Triggered when event is detected on RESET_IN terminal.
WDT Internal event Rising Never 2 Watchdog time-out interrupt: Triggered when watchdog time-out has expired.
RTC_TIMER Internal event Rising Yes
(if INT not masked)
1 Real-time clock timer interrupt: Triggered at programmed regular period of time (every second or minute). Running in ACTIVE, OFF, and SLEEP state, default inactive.
RTC_ALARM Internal event Rising Yes
(if INT not masked)
0 Real-time clock alarm interrupt: Triggered at programmed determinate date and time.
VBUS VBUS (terminal) Rising and falling Yes
(if INT not masked)
INT3 7 VBUS wake-up comparator interrupt. Active in OFF state. Triggered when VBUS present.
GPADC_EOC_SW Internal event N/A Yes
(if INT not masked)
2 GPADC software end of conversion interrupt: Triggered when conversion result is available.
GPADC_AUTO_1 Internal event N/A Yes
(if INT not masked)
1 GPADC automatic periodic conversion 1: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV1_LSB and GPADC_AUTO_CONV1_MSB.
GPADC_AUTO_0 Internal event N/A Yes
(if INT not masked)
0 GPADC automatic periodic conversion 0: Triggered when result of conversion is either above or below (depending on configuration) reference threshold GPADC_AUTO_CONV0_LSB and GPADC_AUTO_CONV0_MSB.
GPIO_7 GPIO_7 (terminal) Rising and/or falling Yes
(if INT not masked)
INT4 7 GPIO_7 rising- or falling-edge detection interrupt
GPIO_6 GPIO_6 (terminal) Rising and/or falling Yes
(if INT not masked)
6 GPIO_6 rising- or falling-edge detection interrupt
GPIO_5 GPIO_5 (terminal) Rising and/or falling Yes
(if INT not masked)
5 GPIO_5 rising- or falling-edge detection interrupt
GPIO_4 GPIO_4 (terminal) Rising and/or falling Yes
(if INT not masked)
4 GPIO_4 rising- or falling-edge detection interrupt
GPIO_3 GPIO_3 (terminal) Rising and/or falling Yes
(if INT not masked)
3 GPIO_3 rising- or falling-edge detection interrupt
GPIO_2 GPIO_2 (terminal) Rising and/or falling Yes
(if INT not masked)
2 GPIO_2 rising- or falling-edge detection interrupt
GPIO_1 GPIO_1 (terminal) Rising and/or falling Yes
(if INT not masked)
1 GPIO_1 rising- or falling-edge detection interrupt
GPIO_0 GPIO_0 (terminal) Rising and/or falling Yes
(if INT not masked)
0 GPIO_0 rising- or falling-edge detection interrupt