JAJSDU8C March 2016 – February 2019 TPS65916
PRODUCTION DATA.
As in every switch-mode-supply design, general layout rules apply:
The goal of these guidelines is a layout that minimizes emissions, maximizes EMI immunity, and maintains a safe operating area (SOA) for the device.
To minimize the spiking at the phase-node for both the high-side (VIN to SWx) and low-side (SWx to PGND), the decoupling of VIN is the most important guideline. Appropriate decoupling and thorough layout should ensure that the spikes never exceed 7V across the high-side and low-side FETs.
Figure 6-9 shows a set of guidelines regarding parasitic inductance and resistance that are recommended.
Table 6-3 lists the maximum allowable parasitic (inductance measured at 100 MHz) and the achievable values in an optimized layout.
CONNECTION | MAXIMUM ALLOWABLE INDUCTANCE | MAXIMUM ALLOWABLE RESISTANCE | OPTIMIZED LAYOUT (EVM) INDUCTANCE | OPTIMIZED LAYOUT (EVM) RESISTANCE | ||
---|---|---|---|---|---|---|
PowerPlane to CIN | N/A | N/A for SOA
Maintain a low resistance value for efficiency |
N/A | N/A for SOA
Maintain a low resistance value for efficiency |
||
CIN to SMPSx_IN | 0.5 nH | 2 mΩ | SMPS1 | 0.2 nH | SMPS1 | 1.1 mΩ |
SMPS2 | 0.2 nH | SMPS2 | 1.6 mΩ | |||
SMPS3 | 0.2 nH | SMPS3 | 1.5 mΩ | |||
SMPS4 | 0.2 nH | SMPS4 | 1.8 mΩ | |||
SMPS5 | 0.2 nH | SMPS5 | 1.5 mΩ | |||
CIN to PGND | 0.5 nH | 2 mΩ | SMPS1 | 0.3 nH | SMPS1 | 0.4 mΩ |
SMPS2 | 0.3 nH | SMPS2 | 0.4 mΩ | |||
SMPS3 | 0.4 nH | SMPS3 | 0.5 mΩ | |||
SMPS4 | 0.3 nH | SMPS4 | 0.6 mΩ | |||
SMPS5 | 0.4 nH | SMPS5 | 0.5 mΩ | |||
SMPSx_SW to inductor | N/A | N/A for SOA
Maintain a low resistance value for efficiency |
N/A | SMPS1 | 1 mΩ | |
SMPS2 | 0.7 mΩ | |||||
SMPS3 | 1 mΩ | |||||
SMPS4 | 0.7 mΩ | |||||
SMPS5 | 1.4 mΩ | |||||
Inductor to COUT | N/A | N/A for SOA
Maintain a low resistance value for efficiency |
N/A | N/A for SOA
Maintain a low resistance value for efficiency |
||
COUT to GND | Use dedicated GND plane to keep inductance low | 1 mΩ | SMPS1 | 0.8 nH | SMPS1 | 0.7 mΩ |
SMPS2 | 0.6 nH | SMPS2 | 0.8 mΩ | |||
SMPS3 | 0.5 nH | SMPS3 | 0.6 mΩ | |||
SMPS4 | 0.4 nH | SMPS4 | 0.6 mΩ | |||
SMPS5 | 0.5 nH | SMPS5 | 0.5 mΩ | |||
GND (CIN) to GND (COUT) | Use dedicated GND plane to keep inductance low | 1 mΩ | Use dedicated GND plane to keep inductance low | mΩ |
Texas Instruments recommends measuring the voltages across the high-side FET (voltage at SMPSx_IN versus SMPSx_SW) and the low-side FET (SMPSx_SW versus PGND) with a high bandwidth, high sampling-rate scope with a low-capacitance probe (ideally a differential probe). Measure the voltages as close as possible to the device pins and verify the amplitude of the spikes. A small-loop ground connection to PGND is essential.
When measuring the voltage difference between the SMPSx_IN and SMPSx_SW pins, there should be a maximum of 7 V when measuring at the pins. Similarly, when measuring the voltage difference between the SMPSx_SW and PGND pins, there should be a maximum of 7 V when measuring at the pins.
For more information on cursor-positioning, see Figure 6-10 and Figure 6-11.