SBVS190E March   2012  – December 2015 TPS7A7300

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configurations
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 User-Configurable Output Voltage
      2. 7.3.2 Traditional Adjustable Configuration
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Soft-Start
      5. 7.3.5 Current Limit
      6. 7.3.6 Enable
      7. 7.3.7 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 ANY-OUT Programmable Output Voltage
        2. 8.2.2.2 Traditional Adjustable Output Voltage
        3. 8.2.2.3 Input Capacitor Requirements
        4. 8.2.2.4 Output Capacitor Requirements
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
    5. 10.5 Estimating Junction Temperature
  11. 11Device And Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, And Orderable Information

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7 Detailed Description

7.1 Overview

The TPS7A7300 belongs to a family of new-generation LDO regulators that uses innovative circuitry to offer very low dropout voltage along with the flexibility of a programmable output voltage.

The dropout voltage for this LDO regulator family is 0.24 V at 3 A. This voltage is ideal for making the TPS7A7300 into a point-of-load (POL) regulator because 0.24 V at 3 A is lower than any voltage gap among the most common voltage rails: 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3 V, and 3.3 V. This device offers a fully user-configurable output voltage setting method. The TPS7A7300 output voltage can be programmed to any target value from
0.9 V to 3.5 V in 50-mV steps.

Another big advantage of using the TPS7A7300 is the wide range of available operating input voltages: from
1.5 V to 6.5 V. The TPS7A7300 also has very good line and load transient response. All these features allow the TPS7A7300 to meet most voltage-regulator needs for under 6-V applications, using only one device so less time is spent on inventory control.

Texas Instruments also offers different output current ratings with other family devices: the TPS7A7100 (1 A) and TPS7A7200 (2 A).

7.2 Functional Block Diagram

TPS7A7300 fbd_bvs136.gif

NOTE:

32R = 1.024 MΩ (that is, 1R = 32 kΩ).

7.3 Feature Description

7.3.1 User-Configurable Output Voltage

Unlike traditional LDO devices, the TPS7A7300 comes with only one orderable part number. There is no adjustable or fixed output voltage option. The output voltage of the TPS7A7300 is selectable in accordance with the names given to the output voltage setting pins: 50 mV, 100 mV, 200 mV, 400 mV, 800 mV, and 1.6 V. For each pin connected to the ground, the output voltage setting increases by the value associated with that pin name, starting from the value of the reference voltage of 0.5 V. Floating the pins has no effect on the output voltage. Figure 24 through Figure 29 show examples of how to program the output voltages.

TPS7A7300 fbd_0p9_bvs189_90.gif Figure 24. 0.9-V Configuration
TPS7A7300 fbd_1p2_bvs189_90.gif Figure 25. 1.2-V Configuration
TPS7A7300 fbd_1p8_bvs189_90.gif Figure 26. 1.8-V Configuration
TPS7A7300 fbd_2p5_bvs189_90.gif Figure 27. 2.5-V Configuration
TPS7A7300 fbd_3p3_bvs189_90.gif Figure 28. 3.3-V Configuration
TPS7A7300 fbd_3p5_bvs189_90.gif Figure 29. 3.5-V Configuration

See Table 1 for a full list of target output voltages and corresponding pin settings. The voltage setting pins have a binary weight; therefore, the output voltage can be programmed to any value from 0.9 V to 3.5 V in 50-mV steps.

Figure 11 and Figure 12 show this output voltage programming performance.

SPACE

NOTE

Any output voltage setting that is not listed in Table 1 is not covered in Electrical Characteristics. For output voltages greater than 3.5 V, use a traditional adjustable configuration (see the Traditional Adjustable Configuration section).

Table 1. User Configurable Output Voltage Setting

VOUT(TARGET)
(V)
50 mV 100 mV 200 mV 400 mV 800 mV 1.6 V VOUT(TARGET)
(V)
50 mV 100 mV 200 mV 400 mV 800 mV 1.6 V
0.9 open open open GND open open 2.25 GND GND open open open GND
0.95 GND open open GND open open 2.3 open open GND open open GND
1 open GND open GND open open 2.35 GND open GND open open GND
1.05 GND GND open GND open open 2.4 open GND GND open open GND
1.1 open open GND GND open open 2.45 GND GND GND open open GND
1.15 GND open GND GND open open 2.5 open open open GND open GND
1.2 open GND GND GND open open 2.55 GND open open GND open GND
1.25 GND GND GND GND open open 2.6 open GND open GND open GND
1.3 open open open open GND open 2.65 GND GND open GND open GND
1.35 GND open open open GND open 2.7 open open GND GND open GND
1.4 open GND open open GND open 2.75 GND open GND GND open GND
1.45 GND GND open open GND open 2.8 open GND GND GND open GND
1.5 open open GND open GND open 2.85 GND GND GND GND open GND
1.55 GND open GND open GND open 2.9 open open open open GND GND
1.6 open GND GND open GND open 2.95 GND open open open GND GND
1.65 GND GND GND open GND open 3 open GND open open GND GND
1.7 open open open GND GND open 3.05 GND GND open open GND GND
1.75 GND open open GND GND open 3.1 open open GND open GND GND
1.8 open GND open GND GND open 3.15 GND open GND open GND GND
1.85 GND GND open GND GND open 3.2 open GND GND open GND GND
1.9 open open GND GND GND open 3.25 GND GND GND open GND GND
1.95 GND open GND GND GND open 3.3 open open open GND GND GND
2 open GND GND GND GND open 3.35 GND open open GND GND GND
2.05 GND GND GND GND GND open 3.4 open GND open GND GND GND
2.1 open open open open open GND 3.45 GND GND open GND GND GND
2.15 GND open open open open GND 3.5 open open GND GND GND GND
2.2 open GND open open open GND

7.3.2 Traditional Adjustable Configuration

For any output voltage target that is not supported in the User-Configurable Output Voltage section, a traditional adjustable configuration with external-feedback resistors can be used with the TPS7A7300. Figure 30 shows how to configure the TPS7A7300 as an adjustable regulator with an equation and Table 2 lists recommended pairs of feedback resistor values.

NOTE

The bottom side of feedback resistor R2 in must be in the range of 27 kΩ to 33 kΩ to maintain the specified regulation accuracy.

TPS7A7300 fbd_adj_bvs189_90.gif Figure 30. Traditional Adjustable Configuration With External Resistors

Table 2. Recommended Feedback-Resistor Values

VOUT(TARGET)
(V)
E96 SERIES R40 SERIES
R1 (kΩ) R2 (kΩ) R1 (kΩ) R2 (kΩ)
1 30.1 30.1 30 30
1.2 39.2 28 43.7 31.5
1.5 61.9 30.9 60 30
1.8 80.6 30.9 80 30.7
1.9 86.6 30.9 87.5 31.5
2.5 115 28.7 112 28
3 147 29.4 150 30
3.3 165 29.4 175 31.5
5 280 30.9 243 27.2

7.3.3 Undervoltage Lockout (UVLO)

The TPS7A7300 uses an undervoltage lockout circuit to keep the output shut off until the internal circuitry is operating properly. The UVLO circuit has a deglitch feature that typically ignores undershoot of the input voltage upon the event of device start-up. Still, a poor input line impedance may cause a severe input voltage drop when the device powers on. As explained in the Input Capacitor Requirements section, the input line impedance must be well-designed.

7.3.4 Soft-Start

The TPS7A7300 has an SS pin that provides a soft-start (slow start) function.

By leaving the SS pin open, the TPS7A7300 performs a soft-start by its default setting.

As shown in Functional Block Diagram, by connecting a capacitor between the SS pin and the ground, the CSS capacitor forms an RC pair together with the integrated 50-kΩ resistor. The RC pair operates as an RC-delay circuit for the soft-start together with the internal 700-µs delay circuit.

The relationship between CSS and the soft-start time is shown in Figure 40 through Figure 42.

7.3.5 Current Limit

The TPS7A7300 internal current limit circuitry protects the regulator during fault conditions. During a current limit event, the output sources a fixed amount of current that is mostly independent of the output voltage. The current limit function is provided as a fail-safe mechanism and is not intended to be used regularly. Do not design any applications to use this current limit function as a part of expected normal operation. Extended periods of current limit operation degrade device reliability.

Powering on the device with the enable pin, or increasing the input voltage above the minimum operating voltage while a low-impedance short exists on the output of the device, may result in a sequence of high-current pulses from the input to the output of the device. The energy consumed by the device is minimal during these events; therefore, there is no failure risk. Additional input capacitance helps to mitigate the load transient requirement of the upstream supply during these events.

7.3.6 Enable

The EN pin switches the enable and disable (shutdown) states of the TPS7A7300. A logic high input at the EN pin enables the device; a logic low input disables the device. When disabled, the device current consumption is reduced.

7.3.7 Power Good

The TPS7A7300 has a power good function that works with the PG output pin. When the output voltage undershoots the threshold voltage VIT(PG) during normal operation, the PG open-drain output turns from a high-impedance state to a low-impedance state. When the output voltage exceeds the VIT(PG) threshold by an amount greater than the PG hysteresis, Vhys(PG), the PG open-drain output turns from a low-impedance state to high-impedance state. By connecting a pullup resistor (usually between OUT and PG pins), any downstream device can receive an active-high enable logic signal.

When setting the output voltage to less than 1.8 V and using a pullup resistor between OUT and PG pins, depending on the downstream device specifications, the downstream device may not accept the PG output as a valid high-level logic voltage. In such cases, place a pullup resistor between IN and PG pins, not between OUT and PG pins.

Figure 18 shows the open-drain output drive capability. The on-resistance of the open-drain transistor is calculated using Figure 18, and is approximately 200 Ω. Any pullup resistor greater than 10 kΩ works fine for this purpose.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

  • The input voltage is at least as high as VIN(MIN).
  • The input voltage is greater than the nominal output voltage added to the dropout voltage.
  • The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold.
  • The output current is less than the current limit.
  • The device junction temperature is less than the maximum specified junction temperature.

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this mode of operation, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device (such as a bipolar junction transistor, or BJT) is in saturation and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations.

7.4.3 Disabled

The device is disabled under the following conditions:

  • The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold.
  • The device junction temperature is greater than the thermal shutdown temperature.

Table 3 lists the conditions that lead to the different modes of operation.

Table 3. Device Functional Mode Comparison

OPERATING MODE PARAMETER
VIN VEN IOUT TJ
Normal mode VIN > VOUT(NOM) + VDO and VIN > VIN(MIN) VEN > VIH(EN) IOUT < I(LIM) TJ < 125°C
Dropout mode VIN < VOUT(NOM) + VDO VEN > VIH(EN) TJ < 125°C
Disabled mode (any true condition disables the device) VEN < VIL(EN) TJ > 160°C