SBVS190E March   2012  – December 2015 TPS7A7300


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configurations
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 User-Configurable Output Voltage
      2. 7.3.2 Traditional Adjustable Configuration
      3. 7.3.3 Undervoltage Lockout (UVLO)
      4. 7.3.4 Soft-Start
      5. 7.3.5 Current Limit
      6. 7.3.6 Enable
      7. 7.3.7 Power Good
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. ANY-OUT Programmable Output Voltage
        2. Traditional Adjustable Output Voltage
        3. Input Capacitor Requirements
        4. Output Capacitor Requirements
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
    4. 10.4 Power Dissipation
    5. 10.5 Estimating Junction Temperature
  11. 11Device And Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, And Orderable Information



10 Layout

10.1 Layout Guidelines

  • To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the board with separate ground planes for IN and OUT, with each ground plane connected only at the GND pin of the device.
  • In addition, the ground connection for the output capacitor must connect directly to the GND pin of the device.
  • Equivalent series inductance (ESL) and ESR must be minimized to maximize performance and ensure stability.
  • Every capacitor must be placed as close as possible to the device and on the same side of the PCB as the regulator itself.
  • Do not place any of the capacitors on the opposite side of the PCB from where the regulator is installed.
  • The use of vias and long traces is strongly discouraged because they may impact system performance negatively and even cause instability.
  • If possible, and to ensure the maximum performance denoted in this product data sheet, use the same layout pattern used for the TPS7A7300 evaluation board, SLAU430.

10.2 Layout Example

TPS7A7300 layout_sbvs189.gif Figure 43. TPS7A7300 Recommended Layout

10.3 Thermal Considerations

The thermal protection feature disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal-protection circuit may cycle on and off. This thermal limit protects the device from damage as a result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature must be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection must trigger at least 35°C above the maximum expected ambient condition of your particular application. This configuration produces a worst-case junction temperature of 125°C at the highest-expected ambient temperature and worst-case load.

The internal-protection circuitry of the TPS7A7300 has been designed to protect against overload conditions. It was not intended to replace proper heatsinking. Continuously running the TPS7A7300 into thermal shutdown degrades device reliability.

10.4 Power Dissipation

Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the tab or pad is critical to avoiding thermal shutdown and ensuring reliable operation.

Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 1:

Equation 1. TPS7A7300 q_pd_bvs064.gif

Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation.

On the VQFN (RGW) package, the primary conduction path for heat is through the exposed pad to the PCB. The pad can be connected to ground or be left floating; however, it must be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 2:

Equation 2. TPS7A7300 q_rth__bvs136.gif

Knowing the maximum RθJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 44.

TPS7A7300 tc_theta_ja_bvs136.gif


θJA value at a board size of 9-in2 (that is, 3-in × 3-in) is a JEDEC standard.
Figure 44. θJA vs Board Size

shows the variation of θJA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and must not be used to estimate actual thermal performance in real application environments.


When the device is mounted on an application PCB, TI strongly recommends using ΨJT and ΨJB, as explained in the Estimating Junction Temperature section.

10.5 Estimating Junction Temperature

Using the thermal metrics ΨJT and ΨJB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 3). For backwards compatibility, an older θJC,Top parameter is listed as well.

Equation 3. TPS7A7300 q_new_metrics_bvs066.gif



Both TT and TB can be measured on actual application boards using a thermo‐gun (an infrared thermometer).

For more information about measuring TT and TB, see the Application Report SBVA025, Using New Thermal Metrics.

TPS7A7300 ai_thermal_measmt_bvs136.gif Figure 45. Measuring Points For TT And TB

By looking at Figure 46, the new thermal metrics (ΨJT and ΨJB) have very little dependency on board size. That is, using ΨJT or ΨJB with Equation 3 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size.

TPS7A7300 tc_psi_jt_jb_bvs136.gif Figure 46. ΨJT And ΨJB vs Board Size

For a more detailed discussion of why TI does not recommend using θJC(top) to determine thermal characteristics, see Application Report SBVA025, Using New Thermal Metrics. For further information, see Application Report SPRA953, Semiconductor and IC Package Thermal Metrics.