JAJSMN7C september   2021  – june 2023 TPS7A94

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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サーマルパッド・メカニカル・データ
発注情報

7.1 Overview

The TPS7A94 is an ultra-low-noise (0.46 μVRMS over 10-Hz to 100-kHz bandwidth), ultra-high PSRR (> 50 dB to 2 MHz), high-accuracy (1%), low-dropout (LDO) linear voltage regulator with an input range of 1.7 V to 5.7 V and an output voltage range from 0 V to VIN – VDO and is fully specified above 0.4 VOUT. This LDO regulator uses innovative circuitry to achieve wide bandwidth and high loop gain, resulting in ultra-high PSRR even when operating under very low operational headroom (VIN – VOUT). At a high level, the device has two main blocks (the current reference and the unity-gain LDO buffer) and a few secondary features (such as the precision enable, current limit, and PG pin).

The current reference is controlled by the NR/SS pin. This pin sets the output voltage with a single resistor, sets the start-up time, and filters the noise generated by the reference and external set resistor.

The unity-gain LDO buffer is controlled by the OUT pin. The ultra-low-noise does not increase with output voltage and provides wideband PSRR. As such, the SNS pin is only used for remote sensing of the load.

The EN_UV pin sets the precision enable feature. Select the optimal input voltage at which the LDO starts at. There are two independent UVLO voltages in this device: the internal IN rail UVLO and the EN_UV pin.

The FB_PG pin sets the current limit and power-good (PG) features. A voltage divider on this pin programs both the current limit and the PG trip point.

An ultra-low-noise current reference (150 μA, typical) is used in conjunction with an external resistor (RNR/SS) to set the output voltage. This process allows the output voltage range to be set from 0.4 V to (VIN – VDO). To achieve this ultra-low noise, an external capacitor CNR/SS (typically 4.7 μF) is placed in parallel to the RNR/SS resistor used to set the output voltage. The unity-gain architecture provides ultra-high PSRR over a wide frequency range without compromising load and line transients.

This regulator offers programmable current-limit, thermal protection, is fully specified from –40°C to +125°C above 0.4 VOUT, and is offered in a thermally efficient 10-pin, 3-mm × 3-mm WSON package.