JAJSMN7C september   2021  – june 2023 TPS7A94

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Board Layout
        2. 8.4.1.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Modules
        2. 9.1.1.2 Spice Models
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 ドキュメントの更新通知を受け取る方法
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 静電気放電に関する注意事項
    7. 9.7 用語集
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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発注情報

8.1.2 Precision Enable (External UVLO)

The precision enable circuit is used to turn the device on and off. This circuit can be used to set an external undervoltage lockout (UVLO) voltage (see Figure 8-6) to turn on and off the device using a resistor divider between IN, EN_UV, and GND.

If VEN_UV ≥ VIH(EN_UV), the regulator is enabled. If VEN_UV ≤ VIL(EN_UV), the regulator is disabled. The EN_UV pin does not incorporate an internal pulldown resistor to GND and must not be left floating. Use the precision enable circuit for this pin to set an external undervoltage lockout (UVLO) input supply voltage to turn on and off the device using a resistor divider between IN, EN_UV, and GND.

GUID-20210409-CA0I-0QG2-LGHN-TXZC4HC6BRGR-low.gif Figure 8-6 Precision EN Used as External UVLO

This external UVLO configuration prevents the LDO from turning on when the input supply voltage is insufficient and places the device in dropout operation.

Using the EN_UV pin as an externally set UVLO allows simple sequencing of cascaded power supplies. An additional benefit is that the EN_UV pin is never left floating. The EN_UV pin does not have an internal pulldown resistor. In addition to the resistor divider, a zener diode can be needed between the EN_UV pin and ground to comply with the absolute maximum ratings on this pin.

When VIN exceeds the targeted VON voltage and the R(BOTTOM) resistor is set, Equation 1 and Equation 2 provide the R(TOP) resistor value and the VOFF voltage at which the input voltage must drop below to disable the LDO.

Equation 1. R(TOP) ≤ R(BOTTOM) × (VON / VIH(EN_UV) - 1)
Equation 2. VOFF < [1 + R(TOP) / R(BOTTOM)] × (VIH(EN_UV) - VHYS(EN_UV))

where:

  • VOFF is the input voltage where the regulator shuts off
  • VON is the voltage where the regulator turns on

Consider the EN_UV current pin when selecting the R(TOP) and R(BOTTOM) values.