SBVS336A September   2021  – May 2022 TPS7A94

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Setting and Regulation
      2. 7.3.2 Ultra-Low Noise and Ultra-High Power-Supply Rejection Ratio (PSRR)
      3. 7.3.3 Programmable Current Limit and Power-Good Threshold
      4. 7.3.4 Programmable Soft Start (NR/SS Pin)
      5. 7.3.5 Precision Enable and UVLO
      6. 7.3.6 Active Discharge
      7. 7.3.7 Thermal Shutdown Protection (TSD)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
      4. 7.4.4 Current-Limit Operation
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Output Voltage Restart (Overshoot Prevention Circuit)
      2. 8.1.2  Precision Enable (External UVLO)
      3. 8.1.3  Undervoltage Lockout (UVLO) Operation
      4. 8.1.4  Dropout Voltage (VDO)
      5. 8.1.5  Power-Good Feedback (FB_PG Pin) and Power-Good Threshold (PG Pin)
      6. 8.1.6  Adjusting the Factory-Programmed Current Limit
      7. 8.1.7  Programmable Soft-Start and Noise-Reduction (NR/SS Pin)
      8. 8.1.8  Inrush Current
      9. 8.1.9  Optimizing Noise and PSRR
      10. 8.1.10 Adjustable Operation
      11. 8.1.11 Paralleling for Higher Output Current and Lower Noise
      12. 8.1.12 Recommended Capacitor Types
      13. 8.1.13 Load Transient Response
      14. 8.1.14 Power Dissipation (PD)
      15. 8.1.15 Estimating Junction Temperature
      16. 8.1.16 TPS7A94EVM-046 Thermal Analysis
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
      2. 10.1.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 Evaluation Modules
        2. 11.1.1.2 Spice Models
      2. 11.1.2 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • DSC|10
サーマルパッド・メカニカル・データ
発注情報

Detailed Design Procedure

In this design example, the device is powered by a dc/dc convertor switching at 1 MHz. The load requires a 3.3-V clean rail with the spectral noise mask versus frequency shown in Figure 8-28 and a maximum load of 500 mA. The typical 10-μF input and output capacitors and 4.7-μF NR/SS capacitors are used to achieve a good balance between fast start-up time and excellent noise and PSRR performance.

GUID-20210413-CA0I-18Z0-FWLR-QCR1QMP7FPNH-low.gif Figure 8-28 Noise Compliance Mask

The output voltage is set using a 22.1-kΩ, thin-film resistor value calculated as described in the Section 8.1.10 section. To set the current limit to a value close to the 750 mA required by the application, and to set the PG threshold to 95%, use Table 8-2 to set the RFB_PG top and bottom resistors values at 1.47 MΩ and 100 kΩ, respectively.

To set the enable and disable voltages for the device, use the precision enable circuit to set the external UVLO voltage levels as follows: VOFF must be < 80 % of VIN, so set VOFF to 3.75 V. VON is calculated using Equation 1 externally to be 4 V by choosing the bottom resistor value for the precision enable to be 100 kΩ, then use Equation 2 to calculate the top resistor to be 1.54 MΩ.

Figure 8-29 shows that the device meets all design noise requirements except for the noise peaking at 900 kHz. However, this noise peaking can be easily attenuated to the required noise level by means of a pi-filter positioned after the LDO. Figure 8-30 shows that this design is very close to the PSRR level at 1 MHz and may require more margin. Fortunately, both requirements are easily achieved by inserting a pi-filter consisting of a ferrite bead and a small capacitor beyond the LDO and before the load; see Figure 8-27.

The ferrite bead was selected to have a very small dc resistance of less than 50 mΩ, 1 A of current rating, and a relatively small footprint. The added pi-filter components have almost no impact on the LDO accuracy performance and no significant increase in the design total cost.

GUID-20210727-CA0I-NNDW-CGNR-MLHSFWNZDSPF-low.gifFigure 8-29 Output Noise vs Frequency
GUID-20210727-CA0I-J5LJ-3V15-3XKGPCRN6R9W-low.gifFigure 8-30 PSRR vs Frequency