JAJSMH6E July   2021  – August 2023 TPS7H5001-SP , TPS7H5002-SP , TPS7H5003-SP , TPS7H5004-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Device Options
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: All Devices
    6. 8.6  Electrical Characteristics: TPS7H5001-SP
    7. 8.7  Electrical Characteristics: TPS7H5002-SP
    8. 8.8  Electrical Characteristics: TPS7H5003-SP
    9. 8.9  Electrical Characteristics: TPS7H5004-SP
    10. 8.10 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  VIN and VLDO
      2. 9.3.2  Start-Up
      3. 9.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 9.3.4  Voltage Reference
      5. 9.3.5  Error Amplifier
      6. 9.3.6  Output Voltage Programming
      7. 9.3.7  Soft Start (SS)
      8. 9.3.8  Switching Frequency and External Synchronization
        1. 9.3.8.1 Internal Oscillator Mode
        2. 9.3.8.2 External Synchronization Mode
        3. 9.3.8.3 Primary-Secondary Mode
      9. 9.3.9  Primary Switching Outputs (OUTA/OUTB)
      10. 9.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 9.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 9.3.12 Pulse Skipping
      13. 9.3.13 Duty Cycle Programmability
      14. 9.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 9.3.15 Hiccup Mode Operation (HICC)
      16. 9.3.16 External Fault Protection (FAULT)
      17. 9.3.17 Slope Compensation (RSC)
      18. 9.3.18 Frequency Compensation
      19. 9.3.19 Thermal Shutdown
    4. 9.4 Device Functional Modes
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Switching Frequency
        2. 10.2.2.2  Output Voltage Programming Resistors
        3. 10.2.2.3  Dead Time
        4. 10.2.2.4  Leading Edge Blank Time
        5. 10.2.2.5  Soft-Start Capacitor
        6. 10.2.2.6  Transformer
        7. 10.2.2.7  Main Switching FETs
        8. 10.2.2.8  Synchronous Rectificier FETs
        9. 10.2.2.9  RCD Clamp
        10. 10.2.2.10 Output Inductor
        11. 10.2.2.11 Output Capacitance and Filter
        12. 10.2.2.12 Sense Resistor
        13. 10.2.2.13 Hiccup Capacitor
        14. 10.2.2.14 Frequency Compensation Components
        15. 10.2.2.15 Slope Compensation Resistor
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

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メカニカル・データ（パッケージ｜ピン）
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発注情報

8.6 Electrical Characteristics: TPS7H5001-SP

TJ = –55°C to 125°C, VIN = 4 V to 14 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MINIMUM ON-TIME AND DEAD TIME
tMIN Minimum on-time LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V 85 ns
TDPS Primary off to secondary on dead time PS = floating, 5 V ≤ VIN ≤ 14 V, 90% of OUTx falling to 10% of SRx rising, OUTx and SRx floating 5 8 11 ns
PS = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V, 90% of OUTx falling to 10% of SRx rising, OUTx and SRx floating 43 50 55
PS = 107 kΩ, 5 V ≤ VIN ≤ 14 V, 90% of OUTx falling to 10% of SRx rising, OUTx and SRx floating 85 100 110
TDSP Secondary off to primary on dead time SP = floating, 5 V ≤ VIN ≤ 14 V, 90% of SRx falling to 10% of OUTx rising, OUTx and SRx floating 5 8 11 ns
SP = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V, 90% of SRx falling to 10% of OUTx rising edge, OUTx and SRx floating 43 50 55
SP = 107 kΩ, 5 V ≤ VIN ≤ 14 V, 90% of SRx falling to 10% of OUTx rising, OUTx and SRx floating 85 100 110
LEADING EDGE BLANK TIME AND DUTY CYCLE
TLEB Leading edge blank time LEB = 10 kΩ, 5 V ≤ VIN ≤ 14 V 12 15 19 ns
LEB = 49.9 kΩ, 5 V ≤ VIN ≤ 14 V 45 50 55
LEB = 110 kΩ, 5 V ≤ VIN ≤ 14 V 85 100 110
DMAX Maximum duty cycle DCL = AVSS 45 48 50 %
DCL = floating, clock duty cycle = 50% 70 75 80
DCL = VLDO 100