JAJSKR9B June   2007  – July 2021 TRS3221E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC Specifications
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Driver Section Electrical Characteristics
    8. 6.8  Driver Section Switching Characteristics
    9. 6.9  Receiver Section Electrical Characteristics
    10. 6.10 Receiver Section Switching Characteristics
    11. 6.11 Auto-Powerdown Section Electrical Characteristics
    12. 6.12 Auto-Powerdown Section Switching Characteristics
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power
      2. 8.3.2 RS232 Driver
      3. 8.3.3 RS232 Receiver
      4. 8.3.4 RS232 Status
    4. 8.4 Device Functional Modes
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Typical Application
    3. 9.3 Design Requirements
    4. 9.4 Detailed Design Procedure
    5. 9.5 Application Curve
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 サポート・リソース
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.10 Receiver Section Switching Characteristics

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 9-1)
PARAMETER TEST CONDITIONS(3) TYP(1) UNIT
tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 7-3

RGT package

 100 ns

DB or PW package

150
tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 7-3

RGT package

 125 ns

DB or PW package

150
ten Output enable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 7-4 200 ns
tsk(p) Pulse skew(2) See Figure 7-3

RGT package

25

 ns

DB or PW package

50
(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Pulse skew is defined as |tPLH  – tPHL| of each channel of the same device.
(3) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.