SLLSFB2 April 2020 TUSB1146
PRODUCTION DATA.
Table 11 lists the TUSB1146 registers. All register offset addresses not listed in Table 11 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Section |
---|---|---|---|
0xA | General_1 | General Register | Go |
0xB | DCI_TXEQ_CTRL | DCI and TX EQ Control | Go |
0x10 | DP01EQ_SEL | DisplayPort Lane 0 and 1 EQ Control | Go |
0x11 | DP23EQ_SEL | DisplayPort Lane 2 and 3 EQ Control | Go |
0x12 | DisplayPort_1 | AUX Snoop Status | Go |
0x13 | DisplayPort_2 | DP Lane Enable/Disable Control | Go |
0x1C | AEQ_CONTROL1 | AEQ Controls | Go |
0x1D | AEQ_CONTROL2 | AEQ Controls | Go |
0x1E | AEQ_LONG | AEQ setting for Long channel | Go |
0x20 | USBC_EQ | EQ control for RX1 and RX2 receivers | Go |
0x21 | SS_EQ | EQ Control for SSTX receiver | Go |
0x22 | USB3_MISC | Misc USB3 Controls | Go |
0x24 | USB_STATUS | USB state machine status | Go |
0x32 | VOD_CTRL | VOD Linearity and AEQ Controls | Go |
0x3B | AEQ_STATUS | Full and Fast AEQ status | Go |
Complex bit access types are encoded to fit into small table cells. Table 12 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
RH | R
H |
Read
Set or cleared by hardware |
Write Type | ||
W | W | Write |
W1S | W
1S |
Write
1 to set |
WS | W | Write |
Reset or Default Value | ||
-n | Value after reset or the default value |