JAJSKS7B April   2021  – March 2022 TXU0204-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Related Products
  6. 6 Pin Configuration and Functions—TXU0204-Q1
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Tsk, TMAX
    7. 7.7  Switching Characteristics, VCCA = 1.2 ± 0.1 V
    8. 7.8  Switching Characteristics, VCCA = 1.5 ± 0.1 V
    9. 7.9  Switching Characteristics, VCCA = 1.8 ± 0.15 V
    10. 7.10 Switching Characteristics, VCCA = 2.5 ± 0.2 V
    11. 7.11 Switching Characteristics, VCCA = 3.3 ± 0.3 V
    12. 7.12 Switching Characteristics, VCCA = 5.0 ± 0.5 V
    13. 7.13 Operating Characteristics
    14. 7.14 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Load Circuit and Voltage Waveforms
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  CMOS Schmitt-Trigger Inputs with Integrated Pulldowns
        1. 9.3.1.1 Inputs with Integrated Static Pull-Down Resistors
      2. 9.3.2  Control Logic (OE) with VCC(MIN) Circuitry
      3. 9.3.3  Balanced High-Drive CMOS Push-Pull Outputs
      4. 9.3.4  Partial Power Down (Ioff)
      5. 9.3.5  VCC Isolation and VCC Disconnect
      6. 9.3.6  Over-Voltage Tolerant Inputs
      7. 9.3.7  Glitch-Free Power Supply Sequencing
      8. 9.3.8  Negative Clamping Diodes
      9. 9.3.9  Fully Configurable Dual-Rail Design
      10. 9.3.10 Supports High-Speed Translation
      11. 9.3.11 Wettable Flanks
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Regulatory Requirements
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 サポート・リソース
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, generators supply all input pulses that have the following characteristics:

  • f = 1 MHz
  • ZO = 50 Ω
  • Δt/ΔV ≤ 1 ns/V

GUID-3D71EDC8-E56A-4C89-B036-A6A0F5521780-low.gif
CL includes probe and jig capacitance.
Figure 8-1 Load Circuit
Table 8-1 Load Circuit Conditions
Parameter VCCO RL CL S1 VTP
tpd Propagation (delay) time 1.1 V – 5.5 V 10 kΩ 5 pF Open N/A
ten, tdis Enable time, disable time 1.1 V – 1.6 V 10 kΩ 5 pF 2 × VCCO 0.1 V
1.65 V – 2.7 V 10 kΩ 5 pF 2 × VCCO 0.15 V
3.0 V – 5.5 V 10 kΩ 5 pF 2 × VCCO 0.3 V
ten, tdis Enable time, disable time 1.1 V – 1.6 V 10 kΩ 5 pF GND 0.1 V
1.65 V – 2.7 V 10 kΩ 5 pF GND 0.15 V
3.0 V – 5.5 V 10 kΩ 5 pF GND 0.3 V
GUID-9BC6F576-5C5E-45C5-9E0D-1F599105FC7C-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 8-2 Propagation Delay
GUID-76FAEEB1-24EC-4ECD-9E88-9F54DEED822D-low.gif
  1. VCCI is the supply pin associated with the input port.
  2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1
Figure 8-3 Input Transition Rise and Fall Rate
GUID-7726EBF8-B2AF-4235-8920-7B11881A5376-low.gif
  1. Output waveform on the condition that input is driven to a valid Logic Low.
  2. Output waveform on the condition that input is driven to a valid Logic High.
  3. VCCO is the supply pin associated with the output port.
  4. VOH and VOL are typical output voltage levels with specified RL, CL, and S1.
Figure 8-4 Enable Time And Disable Time