JAJSMY4 September   2021 UCC14240-Q1


  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Power Ratings
    6. 6.6 Insulation Specifications
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
      2. 7.3.2 Digital I/O ENA and /PG
      3. 7.3.3 Power-Up and Power-Down Sequencing
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. RLIM Resistor Selection
        2. Capacitor Selection
    3. 8.3 System Examples
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information


  • DWN|36

Layout Guidelines

The UCC14240-Q1 integrated isolated power solution simplifies system design and reduces board area usage. Follow these guidelines for proper PCB layout to achieve optimum performance.

  • Place decoupling capacitors as close as possible to the device pins. For the input supply, place the capacitors between pins 6, 7 (VIN) and pins 1, 2, 5, 8–18 (GNDP). For the isolated output supply, place the capacitors between pin 28, 29 (VDD) and pins 19–25, 30–31, 35–36 (VEE). This location is of particular importance to the input decoupling capacitor because this capacitor supplies the transient current associated with the fast switching waveforms of the power drive circuits.
  • Because the device does not have a thermal pad for heat-sinking, the device dissipates heat through the respective GND pins. Ensure that enough copper (preferably a connection to the ground plane) is present on GNDP and VEE pins for best heat-sinking.
  • If space and layer count allow, TI recommends to connect the VIN, GNDP, VDD, and VEE pins to internal ground or power planes through multiple vias. Alternatively, make the traces that are connected to these pins as wide as possible to minimize losses.
  • Minimize capacitive coupling between the RLIM pin and the FBVEE pin by separating the traces while routing, and if possible use a via near the FBVEE pin to route the feedback connection through a different layer.
  • A minimum of four layers is recommended to accomplish a good thermal PCB design. Inner layers can be used to create a high-frequency bypass capacitor between GNDP and VEE, which in turn mitigates radiated emissions.
  • Pay close attention to the spacing between primary ground plane (GNDP) and secondary ground plane (VEE) on the outer layers of the PCB. The effective creepage and or clearance of the system will be reduced if the two ground planes have a lower spacing than that of the UCC14240-Q1 package.
  • To ensure isolation performance between the primary and secondary side, avoid placing any PCB traces or copper below the UCC14240-Q1 module.