JAJSCB0E June 2016 – December 2021 UCC21520
The recommended input supply voltage (VCCI) for the UCC21520 and the UCC21520A is between 3 V and 18 V. The output bias supply voltage (VDDA/VDDB) range depends on which version of UCC21520 one is using. The lower end of this bias supply range is governed by the internal under voltage lockout (UVLO) protection feature of each device. One mustn’t let VDD or VCCI fall below their respective UVLO thresholds (For more information on UVLO see Section 9.3.1). The upper end of the VDDA/VDDB range depends on the maximum gate voltage of the power device being driven by the UCC21520 and the UCC21520A. The UCC21520 and the UCC21520A have a recommended maximum VDDA/VDDB of 25 V.
A local bypass capacitor should be placed between the VDD and VSS pins. This capacitor should be positioned as close to the device as possible. A low ESR, ceramic surface mount capacitor is recommended. It is further suggested that one place two such capacitors: one with a value of ≈10-µF for device biasing, and an additional ≤100-nF capacitor in parallel for high frequency filtering.
Similarly, a bypass capacitor should also be placed between the VCCI and GND pins. Given the small amount of current drawn by the logic circuitry within the input side of the UCC21520 and the UCC21520A, this bypass capacitor has a minimum recommended value of 100 nF.