JAJSCB0E June 2016 – December 2021 UCC21520
For power converter topologies utilizing half-bridges, the dead time setting between the top and bottom transistor is important for preventing shoot-through during dynamic switching.
The UCC21520 dead time specification in the electrical table is defined as the time interval from 90% of one channel’s falling edge to 10% of the other channel’s rising edge (see Figure 8-4). This definition ensures that the dead time setting is independent of the load condition, and guarantees linearity through manufacture testing. However, this dead time setting may not reflect the dead time in the power converter system, since the dead time setting is dependent on the external gate drive turn-on/off resistor, DC-Link switching voltage/current, as well as the input capacitance of the load transistor.
Here is a suggestion on how to select an appropriate dead time for UCC21520:
In the example, DTSetting is set to 250 ns.
It should be noted that the UCC21520 dead time setting is decided by the DT pin configuration (See Section 9.4.2), and it cannot automatically fine-tune the dead time based on system conditions. It is recommended to parallel a ceramic capacitor, 2.2 nF or above, close to the DT pin with RDT to achieve better noise immunity.