JAJSFV5C July 2018 – March 2022 UCC24624
PRODUCTION DATA
With the wide VDD voltage range capability, UCC24624 clamps the gate driver voltage to a maximum level of 11 V to allow fast driving speed, low driving loss, and compatibility with different MOSFETs. The 11-V level is chosen to minimize the conduction loss for non-logic level MOSFETs. The gate-driver voltage clamp is achieved through the regulated REG pin voltage. When the VDD voltage is above 11 V, the linear regulator regulates the REG pin voltage to 11 V, which is also the power supply of the gate driver stage. This way, the MOSFET gate is well clamped at 11 V, regardless of how high the VDD voltage is. When the VDD voltage is getting close to or below the programmed REG pin regulation voltage, UCC24624 can no longer regulate the REG pin voltage. Instead, it enters a pass-through mode where the REG pin voltage follows the VDD pin voltage minus a smaller linear regulator dropout voltage. During this time, the gate driver voltage is lower than its programmed value but still provides the SR driving capability. The UCC24624 is disabled once the REG pin voltage drops below its UVLO OFF level VREGOFF.