JAJSC45C August   2013  – October 2015 UCC27211A


  1. 特長
  2. アプリケーション
  3. 概要
  4. 改訂履歴
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Propagation Delays
    7. 7.7  Switching Characteristics: Delay Matching
    8. 7.8  Switching Characteristics: Output Rise and Fall Time
    9. 7.9  Switching Characteristics: Miscellaneous
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Level Shift
      4. 8.3.4 Boot Diode
      5. 8.3.5 Output Stages
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Input Threshold Type
        2. VDD Bias Supply Voltage
        3. Peak Source and Sink Currents
        4. Propagation Delay
        5. Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報



11 Layout

11.1 Layout Guidelines

To improve the switching characteristics and efficiency of a design, the following layout rules must be followed.

  • Locate the driver as close as possible to the MOSFETs.
  • Locate the VDD – VSS and VHB-VHS (bootstrap) capacitors as close as possible to the device (see Figure 23).
  • Pay close attention to the GND trace. Use the thermal pad of the DRM package as GND by connecting it to the VSS pin (GND). The GND trace from the driver goes directly to the source of the MOSFET, but must not be in the high current path of the MOSFET drain or source current.
  • Use similar rules for the HS node as for GND for the high-side driver.
  • For systems using multiple and UCC27211A devices, TI recommends that dedicated decoupling capacitors be located at VDD-VSS for each device.
  • Care must be taken to avoid placing VDD traces close to LO, HS, and HO signals.
  • Use wide traces for LO and HO closely following the associated GND or HS traces. A width of 60 to 100 mils is preferable where possible.
  • Use as least two or more vias if the driver outputs or SW node must be routed from one layer to another. For GND, the number of vias must be a consideration of the thermal pad requirements as well as parasitic inductance.
  • Avoid LI and HI (driver input) going close to the HS node or any other high dV/dT traces that can induce significant noise into the relatively high impedance leads.

A poor layout can cause a significant drop in efficiency or system malfunction, and it can even lead to decreased reliability of the whole system.

11.2 Layout Example

UCC27211A layout_example_SLUSBL4.gif Figure 23. UCC27211A PCB Layout Example

11.3 Thermal Considerations

The useful range of a driver is greatly affected by the drive-power requirements of the load and the thermal characteristics of the package. For a gate driver to be useful over a particular temperature range, the package must allow for efficient removal of the heat produced while keeping the junction temperature within rated limits. The thermal metrics for the driver package are listed in Thermal Information. For detailed information regarding the table, refer to the Application Note from Texas Instruments entitled Semiconductor and IC Package Thermal Metrics (SPRA953). The UCC27211A device is offered in SOIC (8) and VSON (8). The Thermal Information section lists the thermal performance metrics related to the SOT-23 package.