JAJSE40A October   2017  – February 2018 UCC28780

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      45W、20VのGaN-ACFアダプタの効率
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information of SOIC
    5. 6.5 Thermal Information of WQFN
    6. 6.6 Electrical Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1 BUR Pin (Programmable Burst Mode)
      2. 7.3.2 FB Pin (Feedback Pin)
      3. 7.3.3 VDD Pin (Device Bias Supply)
      4. 7.3.4 REF Pin (Internal 5-V Bias)
      5. 7.3.5 HVG and SWS Pins
      6. 7.3.6 RTZ Pin (Sets Delay for Transition Time to Zero)
      7. 7.3.7 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      8. 7.3.8 RUN Pin (Driver Enable Pin)
      9. 7.3.9 SET Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  Control Law across Entire Load Range
      4. 7.4.4  Adaptive Amplitude Modulation (AAM)
      5. 7.4.5  Adaptive Burst Mode (ABM)
      6. 7.4.6  Low Power Mode (LPM)
      7. 7.4.7  Standby Power Mode (SBP)
      8. 7.4.8  Startup Sequence
      9. 7.4.9  Survival Mode of VDD
      10. 7.4.10 System Fault Protections
        1. 7.4.10.1 Brown-In and Brown-Out
        2. 7.4.10.2 Output Over-Voltage Protection
        3. 7.4.10.3 Over-Temperature Protection
        4. 7.4.10.4 Programmable Over-Power Protection
        5. 7.4.10.5 Peak Current Limit
        6. 7.4.10.6 Output Short-Circuit Protection
        7. 7.4.10.7 Over-Current Protection
        8. 7.4.10.8 Thermal Shutdown
      11. 7.4.11 Pin Open/Short Protections
        1. 7.4.11.1 Protections on CS pin Fault
        2. 7.4.11.2 Protections on HVG pin Fault
        3. 7.4.11.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Turns (NP)
          4. 8.2.2.2.4 Secondary Turns (NS)
          5. 8.2.2.2.5 Turns of Auxiliary Winding (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Clamp Capacitor Calculation
        4. 8.2.2.4 Bleed-Resistor Calculation
        5. 8.2.2.5 Output Filter Calculation
        6. 8.2.2.6 Calculation of ZVS Sensing Network
        7. 8.2.2.7 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 General Considerations
      2. 10.1.2 RDM and RTZ Pins
      3. 10.1.3 SWS Pin
      4. 10.1.4 VS Pin
      5. 10.1.5 BUR Pin
      6. 10.1.6 FB Pin
      7. 10.1.7 CS Pin
      8. 10.1.8 GND Pin
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|16
  • RTE|16
サーマルパッド・メカニカル・データ
発注情報

6.6 Electrical Characteristics

Over operating free-air temperature range, VVDD = 15V, RRDM = 115 kΩ, RRTZ = 140 kΩ, VBUR= 1.2 V, VSET = 0 V, RNTC = 50 kΩ, VVS = 4 V, VSWS = 0 V, IFB = 0 μA, IHVG = 25 μA, and -40 ⁰C < TJ = TA < 125 ⁰C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
BIAS SUPPLY INPUT CURRENT
IRUN(STOP) Supply current, run No switching 2.3 3 mA
IRUN(SW) Supply current, run Switching, IVSL = 0 µA 2.5 3.3 mA
IWAIT Supply current, wait IFB = -85 µA 400 550 µA
ISTART Supply current, start VVDD = VVDD(ON) – 100 mV, VVS = 0 V 70 140 µA
IFAULT Supply current, fault Fault state 265 350 µA
UNDER-VOLTAGE LOCKOUT (UVLO)
VVDD(ON) VDD turn-on threshold VVDD increasing 16.7 17.5 18.2 V
VVDD(OFF) VDD turn-off threshold VVDD decreasing 9.35 9.8 10.4 V
VVDD(PCT) Offset to power cycle for long output voltage overshoot Offset above VVDD(OFF), IFB = -85 μA 0.3 1 1.5 V
VS INPUT
VVSNC Negative clamp level IVSL = -1.25 mA, voltage below ground 170 250 325 mV
VZCD Zero-crossing detection (ZCD) level VVS decreasing 10 30 55 mV
tZC Zero-crossing timeout delay 1.8 2.2 2.7 µs
tD(ZCD) Propagation delay from ZCD high to PWML high VVS step from 4 V to -0.1 V 20 45 ns
IVSB Input bias current VVS = 4 V -0.25 0 0.25 µA
CS INPUT
VCST(MAX) Maximum CS threshold voltage VCS increasing 765 800 825 mV
VCST(MIN) Minimum CS threshold voltage VCS decreasing, IFB = -85 μA 123 150 170 mV
tCSLEB Leading-edge blanking time VSET = 5 V, VCS = 1 V 175 200 225 ns
VSET = 0 V, VCS = 1 V 115 130 145
tD(CS) Propagation delay of CS comparator high to PWML low VCS step from 0 V to 1 V 15 25 ns
KLC Line-compensation current ratio IVSL = -1.25 mA, IVSL / current out of CS pin 22.5 25 27 A/A
RUN, PWML, PWMH
VPWMLH High level of PWML, PWMH, and RUN pins IPWML(H) = -1 mA, IRUN= -1 mA 4.4 5 V
VPWMHH
VRUNH
VPWMLL Low level of PWML, PWMH, and RUN pins IPWML(H) = +1 mA, IRUN = +1 mA 0.5 V
VPWMHL
VRUNL
tRISE Turn-on rise time, 10% to 90%(1) CLOAD = 10 pF 10 ns
tFALL Turn-off fall time, 90% to 10%(1) CLOAD = 10 pF 10 ns
tD(RUN-PWML) Delay from RUN high to PWML high 1.8 5.4 µs
tD(VS-PWMH) Dead-time between VS high and PWMH high VSET = 5 V 44 55 70 ns
tD(PWML-H) Dead-time between PWML low and PWMH high VSET = 0 V 34 42 51 ns
tON(MIN) Minimum on-time of PWML in low power mode VSET = 5 V, IFB = -85 μA, VCS = 1 V 70 90 115 ns
VSET = 0 V, IFB = -85 μA, VCS = 1 V 48 65 80 ns
PROTECTION
VOVP Over-voltage threshold VVS increasing 4.4 4.5 4.6 V
VOCP Over-current threshold VCS increasing 0.97 1.2 1.35
VCST(OPP) Over-power threshold on CS pin IVSL = 0 μA 574 600 627 mV
IVSL = -333 μA 492 545 595
IVSL = -666 μA 426 460 492
IVSL = -1.25 mA 405 425 452
KOPP OPP threshold voltage ratio VCST(OPP) ratio between IVSL = 0 μA and IVSL = -1.25 mA 1.36 1.4 1.44 V/V
tOPP OPP fault timer IFB = 0 A 115 160 200 ms
IVSL(RUN) VS line-sense run current Current out of VS pin increasing 330 365 400 µA
IVSL(STOP) VS line-sense stop current Current out of VS pin decreasing 275 305 335
KVSL VS line-sense ratio IVSL(STOP) / IVSL(RUN) 0.81 0.836 0.85 A/A
tBO Brown-out detection delay time IVSL < IVSL(STOP) 35 60 75 ms
RRDM(TH) RRDM threshold for CS pin fault 41 50 59 kΩ
tCSF1 Max. PWML on time for detecting CS pin fault VSET = 5 V 1.6 2 2.3 µs
tCSF0 Max. PWML on time for detecting CS pin fault RRDM < RRDM(TH) for VSET = 0 V 0.8 1 1.15 µs
tFDR Fault-reset delay timer OCP, OPP, OVP, SCP, or CS pin fault 1 1.5 1.9 s
TJ(STOP) Thermal shut-down temperature Internal junction temperature 125 °C
NTC INPUT
VNTCTH NTC shut-down voltage Voltage decreasing 0.9 1.0 1.1 V
RNTCTH NTC shut-down resistance RNTC decreasing 8.7 9.5 10.3 kΩ
RNTCR NTC recovery resistance RNTC increasing 19.5 21.7 24 kΩ
INTC NTC pull-up current, out of pin RNTC = 12 kΩ 85 105 120 µA
BUR INPUT AND LOW POWER MODE
KBUR-CST Ratio from VBUR to VCST VCST between VCST(OPP1) and 0.7 V 3.9 4 4.13 V/V
fBR(UP) Upper threshold of burst rate frequency in adaptive burst mode(1) 29 34 39 kHz
fBR(LR) Lower threshold of burst rate frequency in adaptive burst mode(1) 21 25 29 kHz
fLPM Burst rate frequency in low power mode 22 25 28 kHz
IBUR Bias current of VBUR offset in LPM 2.1 2.7 3.4 µA
RTZ INPUT
tZ(MAX) Maximum programmable dead-time from PWMH low to PWML high RRTZ = 280 kΩ, IVSL = -1 mA, VSET = 5 V 380 480 565 ns
tZ(MIN) Minimum programmable dead-time from PWMH low to PWML high RRTZ = 78.4 kΩ, IVSL = -1 mA, VSET = 0 V 66 72 86 ns
tZ Dead-time from PWMH low to PWML high IVSL = -150 μA 144 172 205 ns
IVSL = -450 μA 123 150 177 ns
IVSL = -733 μA 110 125 145 ns
KTZ TZ compensation ratio TZ ratio between IVSL = -200 μA and IVSL = -733 μA 1.26 1.4 1.57 s/s
SWS INPUT
VTH(SWS) SWS zero voltage threshold VSET = 5 V 8.8 9 9.6 V
VSET = 0 V 3.7 4 4.3 V
tD(SWS-PWML) Time between SWS low to PWML high VSWS step from 5 V to 0 V 12 28 ns
FB INPUT
IFB(SBP) Maximum control FB current IFB increasing 75 95 µA
VFB(REG) Regulated FB voltage level 4 4.3 4.65 V
RFBI FB input resistance 7 8 9.5 kΩ
REF OUTPUT
VREF REF voltage level IREF = 0 A 4.9 5 5.1 V
IS(REF) Short current of REF pin Short REF pin 8 14 18 mA
VR(LINE) Line regulation of VREF VVDD = 12 V to 35 V -5 7 mV
VR(LOAD) Load regulation of VREF IREF = 0 mA to 1 mA, change in VREF -10 10 mV
HVG OUTPUT
VHVG HVG voltage level IHVG = +/-200 μA, run state 9.7 10.5 11.4 V
ISE(HVG) HVG max sink current during startup VHVG = 13 V, start state 55 90 140 µA
IS(HVG) Short current of HVG pin Short HVG pin 0.4 1 1.6 mA
VHR(LINE) Line regulation of VHVG VVDD = 12 V to 35 V -25 25 mV
VHVG(OV) HVG over voltage threshold 13.0 13.8 14.6 V
RDM INPUT
tDM(MAX) Maximum PWMH pulse width with maximum tuning VSWS = 12 V 6.08 6.76 7.6 µs
tDM(MIN) Minimum PWMH pulse width with minimum tuning VSWS = 0 V 3.05 3.4 3.8 µs
(1) Not tested in protection, and limits guaranteed by design.