JAJSN98E May   2020  – February 2024 UCC5350-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Function
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications for D Package
    7. 6.7  Insulation Specifications for DWV Package
    8. 6.8  Safety-Related Certifications For D Package
    9. 6.9  Safety-Related Certifications For DWV Package
    10. 6.10 Safety Limiting Values
    11. 6.11 Electrical Characteristics
    12. 6.12 Switching Characteristics
    13. 6.13 Insulation Characteristics Curves
    14. 6.14 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, Inverting, and Noninverting Configuration
      1. 7.1.1 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
        4. 8.3.4.4 Active Miller Clamp
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN+ and IN– Input Filter
        2. 9.2.2.2 Gate-Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
      3. 9.2.3 Selecting VCC1 and VCC2 Capacitors
        1. 9.2.3.1 Selecting a VCC1 Capacitor
        2. 9.2.3.2 Selecting a VCC2 Capacitor
        3. 9.2.3.3 Application Circuits with Output Stage Negative Bias
      4. 9.2.4 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Certifications
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 Trademarks
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 用語集
  14. 13Revision History
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.11 Electrical Characteristics

VCC1 = 3.3 V or 5 V, 0.1-µF capacitor from VCC1 to GND1, VCC2= 15 V, 1-µF capacitor from VCC2 to VEE2, CL = 100-pF, TJ = –40°C to +125°C (UCC5350MC-Q1), TJ = –40°C to +150°C (UCC5350SB-Q1), (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCC1 Input supply quiescent current 1.67 2.4 mA
IVCC2 Output supply quiescent current 1.1 1.8 mA
SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VIT+(UVLO1) VCC1 Positive-going UVLO threshold voltage 2.6 2.8 V
VIT– (UVLO1) VCC1 Negative-going UVLO threshold voltage 2.4 2.5 V
Vhys(UVLO1) VCC1 UVLO threshold hysteresis 0.1 V
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (UCC5350MC-Q1)
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 12 13 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 10.3 11 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 1 V
OUTPUT SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS (UCC5350SB-Q1)
VIT+(UVLO2) VCC2 Positive-going UVLO threshold voltage 8.7 9.4 V
VIT–(UVLO2) VCC2 Negative-going UVLO threshold voltage 7.3 8.0 V
Vhys(UVLO2) VCC2 UVLO threshold voltage hysteresis 0.7 V
LOGIC I/O
VIT+(IN) Positive-going input threshold voltage (IN+, IN–) 0.55 × VCC1 0.7 × VCC1 V
VIT–(IN) Negative-going input threshold voltage (IN+, IN–) 0.3 × VCC1 0.45 × VCC1 V
Vhys(IN) Input hysteresis voltage (IN+, IN–) 0.1 × VCC1 V
IIH High-level input leakage at IN+ IN+ = VCC1 40 240 µA
IIL Low-level input leakage at IN– IN– = GND1 –240 –40 µA
IN– = GND1 – 5 V –310 –80
GATE DRIVER STAGE
VOH High-level output voltage (VCC2 - OUT) and (VCC2 - OUTH) IOUT = –20 mA 100 240 mV
VOL Low level output voltage (OUT and OUTL) IN+ = low, IN– = high; IOUT = 20 mA 5 7 mV
IOH Peak source current UCC5350MC, IN+ = high, IN– = low 5 10 A
UCC5350SB, IN+ = high, IN– = low 5 8.5 A
IOL Peak sink current IN+ = low, IN– = high 5 10 A
Active Miller Clamp (UCC5350MC-Q1 only)
VCLAMP Low-level clamp voltage ICLAMP = 20 mA 7 10 mV
ICLAMP Clamp low-level current VCLAMP = VEE2 + 15 V 5 10 A
ICLAMP(L) Clamp low-level current for low output voltage VCLAMP = VEE2 + 2 V 5 10 A
VCLAMP-TH Clamp threshold voltage 2.1 2.3 V
SHORT CIRCUIT CLAMPING
VCLP-OUT Clamping voltage
(VOUT –VCC2)		 IN+ = high, IN– = low, tCLAMP = 10 µs,
IOUT= 500 mA		 1 1.3 V
VCLP-OUT Clamping voltage
( VEE2 – VOUT)		 IN+ = low, IN– = high, tCLAMP = 10 µs,
IOUT = –500 mA		 1.5 V
IN+ = low, IN– = high,
IOUT = –20 mA		 0.9 1
ACTIVE PULLDOWN
VOUTSD Active pulldown voltage on OUT IOUT = 0.1 × IOUT(typ), VCC2 = open 1.8 2.5 V