SLUSCA5B December   2015  – January 2017 UCD3138064A


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Options
    1. 3.1 Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 PMBus/SMBus/I2C Timing
    8. 5.8 Parametric Measurement Information
    9. 5.9 Typical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
    4. 6.4 Feature Description
      1. 6.4.1  System Module
        1. Address Decoder (DEC)
        2. Memory Management Controller (MMC)
        3. System Management (SYS)
        4. Central Interrupt Module (CIM)
      2. 6.4.2  Peripherals
        1. Digital Power Peripherals
          1. Front End
          2. DPWM Module
          3. DPWM Events
          4. High Resolution DPWM
          5. Over Sampling
          6. DPWM Interrupt Generation
          7. DPWM Interrupt Scaling/Range
      3. 6.4.3  Synchronous Rectifier Dead Time Optimization Peripheral
      4. 6.4.4  Automatic Mode Switching
        1. Phase Shifted Full Bridge Example
        2. LLC Example
        3. Mechanism For Automatic Mode Switching
      5. 6.4.5  DPWMC, Edge Generation, IntraMux
      6. 6.4.6  Filter
        1. Loop Multiplexer
        2. Fault Multiplexer
      7. 6.4.7  Communication Ports
        1. SCI (UART) Serial Communication Interface
        2. PMBUS/I2C
        3. SPI
      8. 6.4.8  Timers
        1. 24-Bit Timer
        2. 16-Bit PWM Timers
        3. Watchdog Timer
      9. 6.4.9  General Purpose ADC12
      10. 6.4.10 Miscellaneous Analog
      11. 6.4.11 Brownout
      12. 6.4.12 Global I/O
      13. 6.4.13 Temperature Sensor Control
      14. 6.4.14 I/O Mux Control
      15. 6.4.15 Current Sharing Control
      16. 6.4.16 Temperature Reference
    5. 6.5 Device Functional Modes
      1. 6.5.1 DPWM Modes Of Operation
        1. Normal Mode
        2. Phase Shifting
        3. DPWM Multiple Output Mode
        4. DPWM Resonant Mode
      2. 6.5.2 Triangular Mode
      3. 6.5.3 Leading Edge Mode
    6. 6.6 Memory
      1. 6.6.1 Register Maps
        1. CPU Memory Map and Interrupts
          1. Memory Map (After Reset Operation)
          2. Memory Map (Normal Operation)
          3. Memory Map (System and Peripherals Blocks)
        2. Boot ROM
        3. Customer Boot Program
        4. Flash Management
        5. Synchronous Rectifier MOSFET Ramp and IDE Calculation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. DPWM Initialization for PSFB
          1. DPWM Synchronization
        3. Fixed Signals to Bridge
        4. Dynamic Signals to Bridge
        5. System Initialization for PCM
          1. Use of Front Ends and Filters in PSFB
          2. Peak Current Detection
          3. Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. Device Grounding and Layout Guidelines
        2. Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information



Device Overview


  • 64 kB Program Flash Derivative of UCD3138 Family
    • 2-32 kB Program Flash Memory Banks
    • Supports Execution From 1 Bank, While Programming Another
    • Capability to Update Firmware Without Shutting Down the Power Supply
    • Additional Communication Ports Compared to the UCD3138 (+1 SPI, +1 I2C)
    • Pin-to-Pin Compatible with UCD3138 (SLUSAP2B)
  • Digital Control of up to 3 Independent Feedback Loops
    • Dedicated PID Based Hardware
    • 2-pole/2-zero Configurable
    • Non-Linear Control
  • Soft Start / Stop with and without Prebias
  • Fast Input Voltage Feed Forward Hardware
  • Synchronous Rectifier Dead Time Optimization Peripheral to Use with UCD7138 Synchronous Rectifier Driver
  • Up to 16 MHz Error A/D Converter (EADC)
    • Configurable Resolution as Small as 1 mV/LSB
    • Up to 8x Oversampling
    • Hardware Based Averaging (Up to 8x)
    • 14 bit Effective DAC With 4 Bits of Dither
    • Adaptive Trigger Positioning
  • Up to 8 High Resolution Digital Pulse Width Modulated (DPWM) Outputs
    • 250 ps Pulse Width Resolution
    • 4 ns Frequency and Phase Resolution
    • Adjustable Phase Shift Between Outputs
    • Adjustable Dead-band Between Pairs
    • Cycle-by-Cycle Duty Cycle Matching
    • Up to 2 MHz Switching Frequency
  • Configurable Trailing/Leading/Triangular Modulation
  • Configurable Feedback Control
    • Voltage, Average Current and Peak Current Mode Control
    • Constant Current, Constant Power
  • Configurable FM, Phase Shift Modulation and PWM
  • Fast, Automatic and Smooth Mode Switching
    • Frequency Modulation and PWM
    • Phase Shift Modulation and PWM
    • Frequency Modulation and Phase Shift Modulation
  • High Efficiency and Light Load Management
    • Burst Mode
    • Ideal Diode Emulation
    • Synchronous Rectifier Soft On/Off
    • Low Device Standby Power
  • Primary Side Voltage Sensing
  • Flux and Phase Current Balancing
  • Current Share (Average & Master/Slave)
  • Feature Rich Fault Protection Options
    • 7 Analog / 4 Digital Comparators
    • Cycle-by-Cycle Current Limiting
    • Programmable Blanking Time and Fault Counting
    • External Fault Inputs
  • Synchronization of DPWM Waveforms Between Multiple UCD3138064A Devices
  • 14 channel, 12 bit, 267 ksps General Purpose ADC with Integrated
    • Programmable Averaging Filters
    • Dual Sample and Hold
  • Internal Temperature Sensor
  • Fully Programmable High-Performance 31.25 MHz, 32-bit ARM7TDMI-S Processor
    • 64 kB Program Flash (2-32 kB Banks)
    • 2 kB Data Flash with ECC
    • 4 kB Data RAM
    • 8 kB Boot ROM
    • Firmware Boot-Load in the Field via I2C or UART
  • Communication Peripherals
    • 1 - I2C/PMBus, 1 - I2C (master mode only)
    • 2 - UARTs
    • 1 - SPI
  • UART Auto-baud Rate Adjustment
  • Timer Capture with Selectable Input Pins
  • Built In Watchdog: BOD and POR
  • 64-pin QFN and 48-pin QFN Packages
  • Operating Temperature: –40°C to +125°C
  • Debug interface
    • Code Composer StudioTM with JTAG Interface
    • Fusion Digital PowerTM Designer GUI Support


  • Power Supplies and Telecom Rectifiers
  • Power Factor Correction
  • Isolated DC-DC Modules


The UCD3138064A is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single-chip solution. The UCD3138064A, in comparison to Texas Instruments UCD3138 digital power controller (Section 3), offers 64 kB of program Flash memory (vs 32 kB in UCD3138) and additional options for communication such as SPI and a second I2C port. The availability of 64 kB of program Flash memory in 2-32 kB banks, enables the designers to implement dual images of firmware (e.g. one main image + one back-up image) in the device and the flexibility to execute from either of the banks using appropriate algorithms. It also creates the unique opportunity for the processor to load a new program and subsequently execute that program without interrupting power delivery. This feature allows the end user to add new features to the power supply in the field while eliminating any down-time required to load the new program.

The flexible nature of the UCD3138064A makes it suitable for a wide variety of power conversion applications. In addition, multiple peripherals inside the device have been specifically optimized to enhance the performance of AC/DC and isolated DC/DC applications and reduce the solution component count in the IT and network infrastructure space. The UCD3138064A is a fully programmable solution offering customers complete control of their application, along with ample ability to differentiate their solution. At the same time, TI is committed to simplifying our customers' development effort through offering best in class development tools, including application firmware, Code Composer StudioTM software development environment, and TI’s Fusion Power Development GUI which let customers configure and monitor key system parameters.

At the core of the UCD3138064A controller are the Digital Power Peripherals (DPP). Each DPP implements a high-speed digital control loop consisting of a dedicated Error Analog-to-Digital Converter (EADC), a PID-based 2-pole/general-purpose ADC with up to 14 channels2-zero digital compensator and DPWM outputs with 250-ps pulse width resolution. The device also contains a 12-bit, 267-ksps general-purpose ADC with up to 14 channels, timers, interrupt control, PMBus, I2C, SPI and UART communications ports. The device is based on a 32-bit ARM7TDMI-S RISC microcontroller that performs real-time monitoring, configures peripherals, and manages communications. The ARM microcontroller executes its program out of programmable flash memory as well as on chip RAM and ROM.

In addition to the DPP, specific power management peripherals have been added to enable high efficiency across the entire operating range, high integration for increased power density, reliability, and lowest overall system cost and high flexibility with support for the widest number of control schemes and topologies. Such peripherals include: light load burst mode, synchronous rectification, automatic mode switching, input voltage feed forward, copper trace current sense, ideal diode emulation, constant current constant power control, synchronous rectification soft on and off, peak current mode control, flux balancing, secondary side input voltage sensing, high-resolution current sharing, hardware-configurable soft start with pre bias, as well as several other features. Topology support has been optimized for voltage mode and peak current mode controlled phase shifted full bridge, single and dual phase PFC, bridgeless PFC, hard switched full bridge and half bridge, and LLC half bridge and full bridge.

The UCD3138064A is a functional variant of the UCD3138064A Digital Power Controller that includes significant improvements over the UCD3138064. For a description of the complete changes made in the UCD3138064A, refer to UCD3138064A Migration Guide. The major improvements are:

    The General Purpose ADC has been improved for better accuracy and performance at extreme cold temperatures (–40°C).

    The UART peripheral has been modified to include a hardware based auto-baud rate adjustment feature.

    A new Synchronous Rectifier Dead Time Optimization hardware peripheral has been added. Benefits include:

    • Improved efficiency
    • Reduced synchronous rectifier voltage stresses
    • Shorter development cycle

A Duty Cycle Read Function has been added to improve use in peak current mode.

Device Information(1)

UCD3138064A VQFN (64) 9.00 mm × 9.00 mm
For all available packages, see the orderable addendum at the end of the datasheet.

Functional Block Diagram

UCD3138064A FBD_verA_SLUSCA5.gif Figure 1-1 Functional Block Diagram
UCD3138064A fbd_synchronous_SLUSCA5.gif Figure 1-2 Synchronous Rectifier Peripheral use with Synchronous Rectifier Driver