JAJSG17D June 2014 – August 2018 MSP430FR5986 , MSP430FR5987 , MSP430FR5988 , MSP430FR5989 , MSP430FR59891 , MSP430FR6987 , MSP430FR6988 , MSP430FR6989 , MSP430FR69891
PRODUCTION DATA.
Figure 6-4 shows the port diagram. Table 6-20 summarizes the selection of the pin function.
NOTE:
Functional representation only.PIN NAME (P1.x) | x | FUNCTION | CONTROL BITS AND SIGNALS (1) | ||
---|---|---|---|---|---|
P1DIR.x | P1SEL1.x | P1SEL0.x | |||
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/ VREF-/VeREF- | 0 | P1.0 (I/O) | I: 0; O: 1 | 0 | 0 |
TA0.CCI1A | 0 | 0 | 1 | ||
TA0.1 | 1 | ||||
DMAE0 | 0 | 1 | 0 | ||
RTCCLK(6) | 1 | ||||
A0, C0, VREF-, VeREF- (4)(5) | X | 1 | 1 | ||
P1.1/TA0.2/TA1CLK/COUT/A1/C1/ VREF+/VeREF+ | 1 | P1.1 (I/O) | I: 0; O: 1 | 0 | 0 |
TA0.CCI2A | 0 | 0 | 1 | ||
TA0.2 | 1 | ||||
TA1CLK | 0 | 1 | 0 | ||
COUT(7) | 1 | ||||
A1, C1, VREF+, VeREF+ (4)(5) | X | 1 | 1 | ||
P1.2/TA1.1/TA0CLK/COUT/A2/C2 | 2 | P1.2 (I/O) | I: 0; O: 1 | 0 | 0 |
TA1.CCI1A | 0 | 0 | 1 | ||
TA1.1 | 1 | ||||
TA0CLK | 0 | 1 | 0 | ||
COUT(8) | 1 | ||||
A2, C2 (4)(5) | X | 1 | 1 | ||
P1.3/TA1.2/ESITEST4/A3/C3 | 3 | P1.3 (I/O) | I: 0; O: 1 | 0 | 0 |
TA1.CCI2A | 0 | 0 | 1 | ||
TA1.2 | 1 | ||||
N/A | 0 | 1 | 0 | ||
ESITEST4 | 1 | ||||
A3, C3 (4)(5) | X | 1 | 1 |