SBAA461 December   2020 ADC3541 , ADC3542 , ADC3543 , ADC3544 , ADC3641 , ADC3642 , ADC3643 , ADC3644 , ADC3660 , ADC3681 , ADC3682 , ADC3683

 

  1.   Trademarks
  2. 1Introduction
  3. 2Reduce Data Rates: Optimize Pin Count and Data Rate
    1. 2.1 Parallel CMOS
      1. 2.1.1 Parallel SDR
      2. 2.1.2 Parallel DDR
    2. 2.2 Serial CMOS
      1. 2.2.1 2 Wire
      2. 2.2.2 1 Wire
      3. 2.2.3 0.5 Wire
  4. 3Reduce Data Rates: Decimation
  5. 4Summary
  6. 5References

2.1.1 Parallel SDR

In SDR mode, each data bit corresponds to one CMOS output pin on the ADC. For a 14-bit ADC, there will be 14 resistors at each output pin, and one resistor for the data clock (DCLK) for a total of 15 pins and or resistors.

GUID-20201203-CA0I-6WL3-DWT4-3JMCG0RTWNK0-low.png Figure 2-1 Parallel CMOS: 14 bit SDR Resistors

Also, the DCLK will latch the data on only the rising edge of the DCLK. This means that the data bits and the data clock are toggling at the same rate. For example, if the ADC3541 is sampling at 10 MSPS, the data bits and DCLK are toggling at a frequency of 10 MHz. This is actually the lowest data rate we can achieve without utilizing the on-chip digital decimation features 0f the ADC3541.

Table 2-1 Parallel SDR CMOS Mode
Parallel Interface Max Sampling Rate (MSPS) Data Rate (Mbps) Data Pins/Resistors
SDR 65 65 15
GUID-20201102-CA0I-LQHX-TJ4S-XBPGM6BBPB0T-low.png Figure 2-2 Parallel CMOS SDR Timing Diagram