SBAA528 February   2022 ADC12QJ1600-Q1 , TPS62912 , TPS62913


  1.   Trademarks
  2. 1Introduction and System Description
    1. 1.1 Introduction
      1. 1.1.1 ADC12QJ1600-Q1 Noise and Ripple Requirements
      2. 1.1.2 Power Supply Requirements for Clocks
      3. 1.1.3 TPS62913 Low-Noise and Low-Ripple Buck Converter
    2. 1.2 Block Diagram
    3. 1.3 Design Considerations
  3. 2Tests and Results
    1. 2.1 Test Methodology
    2. 2.2 Test Conditions
    3. 2.3 Test Results
  4. 3Conclusion
  5. 4References
  6.   A Appendix

Power Supply Requirements for Clocks

On the ADC12QJ1600-Q1 evaluation module, an external clock is provided to an ultra low noise PLL which is used for clocking the ADC. Similar to high speed ADCs, higher frequencies command larger supply currents. At the same time, higher frequencies require lower clock jitter and therefore lower phase noise. Phase noise is directly impacted by the power supply noise and ripple. The performance of the TPS62913 is shown in Figure 1-3.

GUID-3720FC54-7987-40F4-BC8F-B9762FA0B594-low.gif Figure 1-3 TPS62913 Output Noise Density vs Frequency for 12Vin to 3.3Vout at 2.2 MHz
Note: BW = 100 Hz to 100 kHz

The TPS62913 has been designed specifically for low noise with the addition of an external noise reduction filter cap, which also provides the means to adjust the softstart time. Using a 470 nF CNR/SS cap provide the noise performance desired and a 5 ms softstart time.