The ADC clock frequency plays an important role in determining the conversion latency values reported in the ADC data sheet. Typically, these latency values are reported with the default clock frequency, f_CLK. For example, Table note #1 in the ADS124S08 conversion latency table states that the sinc³ filter conversion latency values are reported with f_CLK = 4.096 MHz. However, choosing a different clock frequency, f_{CLK_NEW}, proportionally changes the resulting latency time when reported in milliseconds.

Table 5-5 shows the number of t_MOD periods, the default first-conversion latency, and the default ODR values for the ADS124S08 sinc³ filter. Table 5-5 also calculates the first-conversion latency and ODR values when f_{CLK_NEW} = 4.5 MHz, which is the maximum clock frequency allowed by the ADS124S08.

Importantly, the number of t_MOD periods in Table 5-5 is unaffected by changes in the clock frequency. However, the resulting conversion latency decreases while the ODR values increase when f_{CLK_NEW} = 4.5 MHz, enabling faster conversion results.

Changing the clock frequency also impacts the programmable delay. As Table 5-3 shows, the ADS124S08 programmable delay is specified in terms of t_MOD periods. For example, the default delay is 14 ∙ t_MOD, which is 3.42 µs when f_CLK = 4.096 MHz. This delay reduces to 3.11 µs when f_{CLK_NEW} = 4.5 MHz. Ensure that the system still has the required delay when changing the value of the clock frequency.

One final thing to consider about the clock frequency is the tolerance. The clock frequency tolerance changes f_CLK and therefore directly impacts the conversion latency as described throughout this section. For example, the ADS124S08 internal oscillator has a maximum accuracy tolerance of ±1.5%, which translates to a conversion latency variation of ±1.5%. Ultimately, consider how the clock frequency tolerance – whether the clock is internal or external to the ADC – might impact systems with very strict timing constraints.