SBAA553 July   2022

Design Goals

Voltage Source AMC3330 Input Voltage AMC3330 Output Voltage
VA VB Resulting VLL VIN DIFF, MIN VIN DIFF, MAX VOUT DIFF, MIN VOUT DIFF, MAX
277 VAC

∠0°

277 VAC

∠120°

±480 V –1 V +1 V –2 V +2 V

Design Description

This circuit performs a split-tap line-to-line isolated voltage-sensing measurement utilizing the AMC3330 isolated amplifier and a voltage-divider circuit. The line-to-line measurement is taken between two 277 VAC sources that are 120° out of phase. The voltage-divider circuit reduces the line-to-line voltage from ±480 V to ±1 V which matches the input voltage range of the AMC3330. The AMC3330 can measure differential signals of ±1 V with a fixed gain of 2 V/V. The AMC3330 has a differential input impedance of 1.2 GΩ and a low input bias current of 2.5 nA, which support low gain-error and low offset-error signal-sensing in high-voltage applications.

By using the split-tap configuration on a balanced three-phase AC voltage system, two line-to-line voltage measurements are sufficient to measure all three line-to-neutral voltages through derivation.

Design Notes

1. The AMC3330 is optimal for voltage-sensing applications due to its high input impedance and low input bias current, both of which minimize the DC errors. The integrated isolated power supply and bipolar input voltage range make the AMC3330 ideal for AC line-to-line voltage sensing.
2. Verify the linear operation of the system for the desired input signal range. This is verified using simulation in the DC Transfer Characteristics section.
3. Ensure the resistors used in the resistor divider circuit are capable of reducing the source input voltage to the AMC3330 input voltage range of ±1 V.
4. Ensure the resistors used in the resistor divider circuit have sufficient operating current and voltage ratings.
5. Verify that the AMC3330 input current is less than ±10 mA as stated in the absolute maximum ratings table of the data sheet.

Design Steps

1. Calculate the total line-to-line voltage (VLL) between the two 277 VAC sources that are 120° apart.
2. Calculate the ratio of the line-to-line voltage to the input voltage of the AMC3330 for the voltage-divider circuit.
3. Choose 1-MΩ resistors for R1, R2, R1', and R2'. Using the ratio from the previous step and the following voltage-divider equation, solve for the equivalent sensing resistance, Rsense, required to reduce the AMC3330 input voltage to ±1 V.
4. The split-tap configuration requires two equivalent sensing-resistors, RS and RS'. Use the analog engineer's calculator to determine the closest standard value for RS and RS'.
5. Calculate the current flowing through the voltage-divider circuit from the voltage source to ensure that the power dissipation does not exceed the ratings of the resistor. For additional details, see Considerations for High Voltage Measurements.
6. Since the gain of the voltage divider is $\frac{1}{480}\phantom{\rule{0ex}{0ex}}$ and the gain of the AMC3330 is 2, the output voltage can be calculated for an input voltage of 480 V using the transfer function equation, ${V}_{OUT}=Gain×{V}_{IN}$ .

DC Transfer Characteristics

The following graph shows the simulated differential output of the AMC3330 for a ±800-V input. The output voltage is about 2 V for an input voltage of 480 V, as calculated on the previous page.

AC Transfer Characteristics

The simulated gain is –47.62 dB which closely matches the expected gain for the voltage divider and AMC3330.

Simulation Results

The following simulation shows the input and output signals of the AMC3330.

Design References

Design Featured Isolated Op Amp

AMC3330
Input Voltage range ±1 V
Nominal Gain

2

Input Resistance

0.8 GΩ (typ)

Small Signal Bandwidth 375 kHz
Input Offset Voltage and Drift ±0.3 mV (max), ±4 µV/°C (max)
Gain Error and Drift ±0.2% (max), ±45 ppm/°C (max)
Nonlinearity and Drift 0.02% (max), ±0.4 ppm/°C (typ)
Isolation Transient Overvoltage 6 kVPEAK
Working Voltage 1.2 kVRMS
Common-mode transient immunity, CMTI 85 kV/µs (min)
AMC3330

Design Alternate Isolated Op Amp

ISO224B
VDD1 4.5 V–18 V
VDD2 4.5 V–5.5 V
Input Voltage range ±12 V
Nominal Gain
VOUT Differential ±4 V on output common-mode of VDD2 / 2
Input Resistance 1.25 MΩ (typ)
Small Signal Bandwidth 275 kHz
Input Offset Voltage and Drift ±5 mV (max), ±15 µV/°C (max)
Gain Error and Drift ±0.3% (max), ±35 ppm/°C (max)
Nonlinearity and Drift 0.01% (max), ±0.1 ppm/°C (typ)
Isolation Transient Overvoltage 7 kVPEAK
Working Voltage 1.5 kVRMS
Common-mode transient immunity, CMTI 55 kV/µs (min)
ISO224