SBAU392A July   2022  – January 2023 AFE7950 , TRF1208

 

  1.   TRF1208-AFE7950-EVM Evaluation Module User's Guide
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 Hardware
      1. 1.1.1 Recommended Test Environment
      2. 1.1.2 Required Hardware
    2. 1.2 Required Software
      1. 1.2.1 Software Installation Sequence
      2. 1.2.2 Software Installation Checks
    3. 1.3 Signal Chain of the EVM Board
  4. 2Hardware Setup (TSW14J56 Used as an Example)
    1. 2.1 Power Supply Setup
    2. 2.2 TRF1208-AFE7950-EVM and TSW14J56 EVM Connections
    3. 2.3 RF Test Equipment Setup
  5. 3Latte Overview
    1. 3.1 Latte User Interface
    2. 3.2 Useful Latte Short-Cuts
  6. 4TRF1208-AFE7950-EVM Automatic Configuration
    1. 4.1 Steps to Start Automatic Configuration
    2. 4.2 TXDAC Evaluation
    3. 4.3 RXADC and FBADC Evaluation
  7. 5Status Check and Troubleshooting Guidelines
    1. 5.1 TRF1208-AFE7950-EVM Status Indicators
    2. 5.2 TSW14J56 EVM
  8. 6TRF1208-AFE7950-EVM Manual Configuration
    1. 6.1 TSW14J5x DAC Pattern Setup
    2. 6.2 Connect Latte to Board
    3. 6.3 Compile Libraries
    4. 6.4 Program TRF1208-AFE7950-EVM
    5. 6.5 Modify Configuration
      1. 6.5.1 Data Rate and JESD Parameters
      2. 6.5.2 Data Converter Clocks Settings
  9. 7Setup the TSW14J5x With the HSDC Pro
    1. 7.1 DAC Pattern Setup and Send
    2. 7.2 DAC Synchronization Check
    3. 7.3 ADC Data Capture
    4. 7.4 ADC Synchronization Check
  10. 8Revision History

4.3 RXADC and FBADC Evaluation

  1. Before starting the RXADC and FBADC performance capture, the test option of the HSDC PRO must be setup. Go to Test Options to enter the Filter Parameters menu. By default, there are 25 bins to remove on either side of fundamental and 25 bins near DC to remove. As shown in Figure 4-9, change the number of bins to remove on either side of fundamental to 100 bins.
    1. With 245.76 MSPS of data rate for RXADC at 16384 sample points, this removes 1.5 MHz of bins on either side of the fundamental.
    2. With 491.52 MSPS of data rate for FBADC at 16384 sample points, this removes 3.0 MHz of bins on either side of the fundamental.
    3. The number of bins to be removed is a standard recommendation from TI to remove the effect of the ADC sampling clock in-band phase noise from affecting the broadband noise used to calculate the SNR through the FFT engine. The number of bins must be adjusted based on the end-application standard.
    GUID-AEEA934A-7164-4089-9F5C-B5AB4D205D8B-low.png Figure 4-9 HSDC PRO ADC Performance FFT Binning Configuration
  2. Connect the RF signal generator output to J3 (RXA_IN), J1 (RXB_IN), and J4 (RXC_IN) to capture the RF input to the ADC. On the High-Speed Data Converter Pro, press the Capture button to capture the ADC data.
  3. Feed in a tone of 10 MHz offset from the channel frequency. For example, feed 2310 MHz to RXA_IN, 5010 MHz to RXB_IN, and 6010 MHz to FB1_IN. Set the signal level to get about -4 dBFS at the ADC output. Since the gain is different for various channels, the signal generator's output levels will be different.
    1. RXA_IN is Channel 1 and 2 in FFT Channel Selection
    2. RXB_IN is Channel 3 and 4 in FFT Channel Selection
    3. FB1_IN is Channel 1 and 2 in FFT under FB mode Channel Selection
  4. Similarly, feed 8010 MHz to RXC_IN and 6010 MHz to FB2_IN. Set the signal level to get about -4 dBFS at ADC output.
    1. RXC_IN is Channel 5 and 6 in FFT Channel Selection
    2. FB2_IN is Channel 3 and 4 in FFT under FB mode Channel Selection
  5. For Feedback ADC, execute the following commands or execute AFE79xx_FB_Capture.py through the F5 key. 
    1. ###### Configure FB-ADC 
####################################################
AFE.TOP.overrideTdd(0,3,0)
hsdcparam.fb.Datarate=sysParams.FadcFb/sysParams.ddcFactorFb[0]*1e6confighsdcpro().fb()