SBAU392A July   2022  – January 2023 AFE7950 , TRF1208

 

  1.   TRF1208-AFE7950-EVM Evaluation Module User's Guide
  2.   Trademarks
  3. 1EVM Overview
    1. 1.1 Hardware
      1. 1.1.1 Recommended Test Environment
      2. 1.1.2 Required Hardware
    2. 1.2 Required Software
      1. 1.2.1 Software Installation Sequence
      2. 1.2.2 Software Installation Checks
    3. 1.3 Signal Chain of the EVM Board
  4. 2Hardware Setup (TSW14J56 Used as an Example)
    1. 2.1 Power Supply Setup
    2. 2.2 TRF1208-AFE7950-EVM and TSW14J56 EVM Connections
    3. 2.3 RF Test Equipment Setup
  5. 3Latte Overview
    1. 3.1 Latte User Interface
    2. 3.2 Useful Latte Short-Cuts
  6. 4TRF1208-AFE7950-EVM Automatic Configuration
    1. 4.1 Steps to Start Automatic Configuration
    2. 4.2 TXDAC Evaluation
    3. 4.3 RXADC and FBADC Evaluation
  7. 5Status Check and Troubleshooting Guidelines
    1. 5.1 TRF1208-AFE7950-EVM Status Indicators
    2. 5.2 TSW14J56 EVM
  8. 6TRF1208-AFE7950-EVM Manual Configuration
    1. 6.1 TSW14J5x DAC Pattern Setup
    2. 6.2 Connect Latte to Board
    3. 6.3 Compile Libraries
    4. 6.4 Program TRF1208-AFE7950-EVM
    5. 6.5 Modify Configuration
      1. 6.5.1 Data Rate and JESD Parameters
      2. 6.5.2 Data Converter Clocks Settings
  9. 7Setup the TSW14J5x With the HSDC Pro
    1. 7.1 DAC Pattern Setup and Send
    2. 7.2 DAC Synchronization Check
    3. 7.3 ADC Data Capture
    4. 7.4 ADC Synchronization Check
  10. 8Revision History

4 TRF1208-AFE7950-EVM Automatic Configuration

This section guides the user through the sequence of steps to automatically bring up the TRF1208-AFE7950-EVM through the automation python routine. The example used in this section will be the default TRF1208-AFE7950-EVM Mode 1. Table 4-1 lists the default Mode 1 configuration overview.

Table 4-1 TRF1208-AFE7950-EVM Mode 1 Configuration Overview
ModeDefault Programming
TX (transmitter)4 TXDACs are enabled, DSA = 0, LMFSHd_2TX = 44210, 6 × interpolation, 491.52-MSPS data rate
RX (receiver)4 RXADCs are enabled, DSA = 0, LMFSHd_2RX = 24410, 12 × decimation, 245.76-MSPS data rate
FBRX (feedback receiver)2 FBADCs are enabled, DSA = 0, LMFSHd_1FB = 22210, 6 × decimation, 491.52-MSPS data rate
SerDes8 lanes running at 9830.4 Mbps
Data Converter Clock RatesFRXADC = 2949.12 MSPS, FFBADC = 2949.12 MSPS, FTXDAC = 8847.36 MSPS
StatusRX AGC is disabled, RX, TX DSA step impairments is uncorrected, DAC in interleaved mode

Table 4-2, Table 4-3, and Table 4-4 list the TSW14J5x INI files used to evaluate the RXADC, FBADC, and the TXDAC portion of the AFE79xx. The tables also list the associated channel mapping with respect to the TRF1208-AFE7950-EVM.

Table 4-2 RXADC TW14J5x INI Mapping (AFE79xx_2x2RX_24410)
ADC Channel Number in HSDC PRO ADC Panel(1)TRF1208-AFE7950-EVM ConnectorAssociated AFE79xx Input
1,2J3, RXA_IN1RX
3,4J1, RXB_IN2RX
5,6J4, RXC_IN3RX
7,8J2, RXD_IN4RX
(1) For complex quadrature output (I/Q) of the RXADC, the odd number is the real channel, while the even number is the imaginary channel.
Table 4-3 FBADC TW14J5x INI Mapping (AFE79xx_1x2FB_44210)
ADC Channel Number in HSDC PRO ADC Panel(1)TRF1208-AFE7950-EVM ConnectorAssociated AFE79xx Input
1,2J6, FB1_IN1FB
3,4J5 and J11, FB2_IN2FB
(1) For complex quadrature output (I/Q) of the FBADC, the odd number is the real channel, while the even number is the imaginary channel.
Table 4-4 TXDAC TSW14J5x INI Mapping (AFE79xx_2x2TX_44210)
DAC Channel Number in HSDC PRO DAC Panel(1)AFE79xx EVM ConnectorAssociated AFE79xx Input
1,2J10, TXA_OUT1TX
3,4J7, TXB_OUT2TX
5,6J9, TXC_OUT3TX
7,8J8, TXD_OUT4TX
(1) For complex quadrature output (I/Q) of the TXDAC, the odd number is the real channel, while the even number is the imaginary channel.