An NMOS/PMOS parallel switch consists of an n-channel pass transistor in parallel with ap-channel pass transistor. Figure 3-3 shows the basic structure of an NMOS/PMOS parallel switch. In an n-channel MOSFET, the source-to-drain resistance is low when the drain voltage is less than V_G – V_T, where V_G is the gate voltage. In a p-channel MOSFET, the source-to-drain resistance is low when the source voltage is greater than V_T + V_G. with the parallel combination of n-channel and p-channel pass transistors, the source-to-drain, or channel resistance, can be lowered for the entire input voltage range from 0 V to V_G. When OE is low, V_G in NMOS/PMOS parallel switch is V_CC, and signals ranging from 0 V to V_CC can be passed through this switch. Figure 3-4 shows the general shape of the r_on versus V_I characteristics of a typical NMOS/PMOS parallel switch, as well as the NMOS and PMOS characteristics. The shape of r_on vs V_I curve may be different, depending on the structures of NMOS and PMOS. The disadvantage of the NMOS/PMOS parallel switch is that the input and output capacitances increase due to the additional source and drain area of the combined transistors.

Figure 3-3 Basic Structure of an NMOS/PMOS Parallel Switch

Figure 3-4 r_on vs V_I Characteristics of a Typical NMOS/PMOS Parallel Switch (V_CC = 5 V)