SLAAE22 June 2021 DAC63204

- The
*DACx3204 12-Bit, 10-Bit, and 8-Bit, Quad Voltage and Current Output Smart DACs With Auto-Detected I2C, PMBus™, or SPI Interface Data Sheet*recommends using a 100-nF decoupling capacitor for the VDD pin and a 1.5-µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal LDO. Place these capacitors close to the device pins. - There are three reference options for the DAC53204:
- An external reference of 1.7 V to VDD can be applied to the VREF pin of the device. Connect a 100nF capacitor between VREF and AGND when using the external reference. Use a pullup resistor to VDD when the external reference is not used.
- There is a precision 1.21 V reference with ×1.5, ×2, ×3, and ×4 gain options.
- VDD can be used as a reference.

- The nominal voltage of the SMPS is set by
resistors R
_{1}and R_{2}. The SMPS uses an internal 600-mV reference voltage at the FB pin to determine the voltage at the output. Calculate R_{1}and R_{2}using the following equations:${R}_{1}=\frac{{V}_{NOMINAL}-{V}_{FB}}{{I}_{NOMINAL}}$${R}_{2}=\frac{{R}_{1}\times {V}_{FB}}{{V}_{NOMINAL}-{V}_{FB}}$A nominal current of 100µA through R_{1}and R_{2}and 3.3 V nominal output voltage will be used. With these values the equations become:${R}_{1}=\frac{3.3V-0.6V}{100\mu A}=27k\Omega $${R}_{2}=\frac{27k\Omega \times 0.6V}{3.3V-0.6V}=6k\Omega $ - To achieve the desired margin, the DAC53204 must
sink or source additional current through R
_{1}. This current (I_{MARGIN}) is calculated by:${I}_{MARGIN}=\frac{{V}_{NOMINAL}\times \left(1+MARGIN\right)-{V}_{FB}}{{R}_{1}}-{I}_{NOMINAL}$For a ±10% margin, the equation becomes:${I}_{MARGIN}=\frac{3.3V\times \left(1+0.10\right)-0.6V}{27k\Omega}-100\mu A=12\mu A$ - The voltage output of the DAC53204 is turned into
a current through the series resistor R
_{3}. R_{3}is calculated by:${R}_{3}=\frac{\left({V}_{DAC}-{V}_{FB}\right)}{{I}_{MARGIN}}$Avoid DAC codes near zero- and full-scale when determining the DAC output voltage range to avoid the zero- and full-scale errors at these codes. This design uses the internal 1.21 V reference with a gain of ×1.5 giving a full-scale voltage of 1.82 V. The DAC53204 has a max zero-code error of 15mV, so a 20-mV minimum output is a safe choice. The maximum output becomes:${V}_{DAC,MAX}=\left({V}_{REF,DAC}\times GAIN\right)-{V}_{FB}-{V}_{DAC,MIN}$${V}_{DAC,MAX}=\left(1.21V\times 1.5\right)-0.6-20mV=1.2V$With this DAC range, R3 becomes:${R}_{3}=\frac{\left(1.2V-0.6V\right)}{12\mu A}=50k\Omega $ - The DAC codes for
V
_{DAC,MAX}and V_{DAC,MIN}are stored in the DAC-MARGIN-HIGH and DAC-MARGIN-LOW registers. The codes programmed to these registers, in decimal, is calculated using:$DAC\_MARGIN\_HIGH=\frac{{V}_{DAC,MAX}}{{V}_{REF}\times GAIN}\times 1024$$DAC\_MARGIN\_LOW=\frac{{V}_{DAC,MIN}}{{V}_{REF}\times GAIN}\times 1024$The equations become:$DAC\_MARGIN\_HIGH=\frac{1.2V}{1.21V\times 1.5}\times 1024=677d$$DAC\_MARGIN\_LOW=\frac{20mV}{1.21V\times 1.5}\times 1024=11.2d$This is rounded to 677d and 11d to give a V

_{DAC,MAX}of 1.2 V and a V_{DAC,MIN}of 19.5mV. - Using a 1.21-V reference with a ×1.5 gain and the 10-bit DAC53204, the LSB size, or step size between each code, is about 1.8mV. Using lower reference voltages decreases the LSB size and thus increases the resolution of V
_{DAC,MAX}and V_{DAC,MIN}. - In this design, GPI is used for
Margin High, Low function. A high on GPI sets the DAC output to
V
_{DAC,MAX}and the SMPS V_{OUT}to margin low, or 2.97 V. A low on GPI sets the DAC output to V_{DAC,MIN}and the SMPS V_{OUT}to margin high, or 3.63V. - The DAC53204 can be programmed with the initial register settings described in the Register Settings section using I2C or SPI. The initial register settings can be saved in the NVM by writing a 1 to the NVM-PROG field of the COMMON-TRIGGER register. After programming the NVM, the device loads all registers with the values stored in the NVM after a reset or a power cycle.