SLAAE22 June   2021

# Design Notes

1. The DACx3204 12-Bit, 10-Bit, and 8-Bit, Quad Voltage and Current Output Smart DACs With Auto-Detected I2C, PMBus™, or SPI Interface Data Sheet recommends using a 100-nF decoupling capacitor for the VDD pin and a 1.5-µF or greater bypass capacitor for the CAP pin. The CAP pin is connected to the internal LDO. Place these capacitors close to the device pins.
2. There are three reference options for the DAC53204:
1. An external reference of 1.7 V to VDD can be applied to the VREF pin of the device. Connect a 100nF capacitor between VREF and AGND when using the external reference. Use a pullup resistor to VDD when the external reference is not used.
2. There is a precision 1.21 V reference with ×1.5, ×2, ×3, and ×4 gain options.
3. VDD can be used as a reference.
3. The nominal voltage of the SMPS is set by resistors R1 and R2. The SMPS uses an internal 600-mV reference voltage at the FB pin to determine the voltage at the output. Calculate R1 and R2 using the following equations:
${R}_{1}=\frac{{V}_{NOMINAL}-{V}_{FB}}{{I}_{NOMINAL}}$
${R}_{2}=\frac{{R}_{1}×{V}_{FB}}{{V}_{NOMINAL}-{V}_{FB}}$
A nominal current of 100µA through R1 and R2 and 3.3 V nominal output voltage will be used. With these values the equations become:
${R}_{1}=\frac{3.3V-0.6V}{100µA}=27k\Omega$
${R}_{2}=\frac{27k\Omega ×0.6V}{3.3V-0.6V}=6k\Omega$
4. To achieve the desired margin, the DAC53204 must sink or source additional current through R1. This current (IMARGIN) is calculated by:
${I}_{MARGIN}=\frac{{V}_{NOMINAL}×\left(1+MARGIN\right)-{V}_{FB}}{{R}_{1}}-{I}_{NOMINAL}$
For a ±10% margin, the equation becomes:
${I}_{MARGIN}=\frac{3.3V×\left(1+0.10\right)-0.6V}{27k\Omega }-100µA=12µA$
5. The voltage output of the DAC53204 is turned into a current through the series resistor R3. R3 is calculated by:
${R}_{3}=\frac{\left({V}_{DAC}-{V}_{FB}\right)}{{I}_{MARGIN}}$
Avoid DAC codes near zero- and full-scale when determining the DAC output voltage range to avoid the zero- and full-scale errors at these codes. This design uses the internal 1.21 V reference with a gain of ×1.5 giving a full-scale voltage of 1.82 V. The DAC53204 has a max zero-code error of 15mV, so a 20-mV minimum output is a safe choice. The maximum output becomes:
${V}_{DAC,MAX}=\left({V}_{REF,DAC}×GAIN\right)-{V}_{FB}-{V}_{DAC,MIN}$
${V}_{DAC,MAX}=\left(1.21V×1.5\right)-0.6-20mV=1.2V$
With this DAC range, R3 becomes:
${R}_{3}=\frac{\left(1.2V-0.6V\right)}{12µA}=50k\Omega$
6. The DAC codes for VDAC,MAX and VDAC,MIN are stored in the DAC-MARGIN-HIGH and DAC-MARGIN-LOW registers. The codes programmed to these registers, in decimal, is calculated using:
$DAC_MARGIN_HIGH=\frac{{V}_{DAC,MAX}}{{V}_{REF}×GAIN}×1024$
$DAC_MARGIN_LOW=\frac{{V}_{DAC,MIN}}{{V}_{REF}×GAIN}×1024$
The equations become:
$DAC_MARGIN_HIGH=\frac{1.2V}{1.21V×1.5}×1024=677d$
$DAC_MARGIN_LOW=\frac{20mV}{1.21V×1.5}×1024=11.2d$

This is rounded to 677d and 11d to give a VDAC,MAX of 1.2 V and a VDAC,MIN of 19.5mV.

7. Using a 1.21-V reference with a ×1.5 gain and the 10-bit DAC53204, the LSB size, or step size between each code, is about 1.8mV. Using lower reference voltages decreases the LSB size and thus increases the resolution of VDAC,MAX and VDAC,MIN.
8. In this design, GPI is used for Margin High, Low function. A high on GPI sets the DAC output to VDAC,MAX and the SMPS VOUT to margin low, or 2.97 V. A low on GPI sets the DAC output to VDAC,MIN and the SMPS VOUT to margin high, or 3.63V.
9. The DAC53204 can be programmed with the initial register settings described in the Register Settings section using I2C or SPI. The initial register settings can be saved in the NVM by writing a 1 to the NVM-PROG field of the COMMON-TRIGGER register. After programming the NVM, the device loads all registers with the values stored in the NVM after a reset or a power cycle.