SLAAEQ8 February   2025 MSPM0C1103 , MSPM0C1103-Q1 , MSPM0C1104 , MSPM0C1104-Q1 , MSPM0C1105 , MSPM0C1106 , MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G1518 , MSPM0G1519 , MSPM0G3105 , MSPM0G3105-Q1 , MSPM0G3106 , MSPM0G3106-Q1 , MSPM0G3107 , MSPM0G3107-Q1 , MSPM0G3505 , MSPM0G3505-Q1 , MSPM0G3506 , MSPM0G3506-Q1 , MSPM0G3507 , MSPM0G3507-Q1 , MSPM0G3518 , MSPM0G3518-Q1 , MSPM0G3519 , MSPM0G3519-Q1 , MSPM0H3216 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2227 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Laser Speckle Reduction
    2. 1.2 MSPM0 Requirements
  5. 2PWM
    1. 2.1 PWM Implementation
    2. 2.2 PWM Test Result
  6. 3PWM and GPIO
    1. 3.1 PWM and GPIO Implementation
    2. 3.2 Interrupt Time Calibration
    3. 3.3 PWM and GPIO Test Result
  7. 4Timer and GPIO
    1. 4.1 Timer and GPIO Implementation
  8. 5Summary
  9. 6References

1.2 MSPM0 Requirements

In this application note, use DRV8847 to control two coils, and each coil controls the optical machine to vibrate on the X-axis and Y-axis, respectively. By controlling the vibration intensity and phase of each coil, DRV8847 can control the vibration direction and distance of the optical machine in the X-Y plane.

DRV8847 is a dual H-bridge motor driver with current regulation and independent half-bridge con. Figure 1-1 is two groups of PWM waveform signals that using to drive two coils. For the procedure that DRV8847 processes these PWM signals, refer to DRV8847 block diagram and DRV8847 Dual H-Bridge Motor Driver data sheet.

PWM Waveform Figure 1-1 PWM Waveform
  • PWM0+ and PWM0- are used to drive coil0.
  • PWM1+ and PWM1- are used to drive coil1.
  • pd0 is the phase difference between PWM0+ and PWM0-, fixed value 180°.
  • pd1 is the phase difference between PWM1+ and PWM1-, fixed value 180°.
  • pd is the phase difference between PWM0 and PWM1, adjustable from -90° to 90°.
  • dc0 is the duty cycle of PWM0+ and PWM0-, adjustable from 0% to 100%.
  • dc1 is the duty cycle of PWM1+ and PWM1-, adjustable from 0% to 100%.

Depending on the device selection, there are multiple ways to generate the above PWM waveform. The main peripherals used include Timer, Event and GPIO. Table 1-1 is the introduction and peripherals used of different methods. For detailed description, please refer to each method's section.

Table 1-1 LSR Control Methods Summary
Method Peripherals MSPM0 Device Support Description
PWM Timer * 4 MSPM0 L and G series Hardware method.
PWM and GPIO Timer *3
GPIO * 1		 MSPM0 C series Hardware and software mixed control.
Timer and GPIO Timer * 1
GPIO * 4		 MSPM0 C, L and G series Software method, high CPU clock is better for precise control.
Note: Hardware implement requires an event channel to trigger between event publisher and event subscriber, the delay of event trigger various from peripherals' power domain and peripherals' type. This kind of event delay is fixed, a fixed offset can be considered to be added to timer's CC (capture and compare) value if high-precision control is required. This suggestion applies to both event between two timers and between GPIO and timer.
Note: MSPM0 can output a variety of PWM signals based on timer peripheral, by using hardware timer with PWM or software IO control. MSPM0's timer support 4 or 2 CCs (capture and compare channel) and each CC can be used to output a PWM waveform or trigger a fixed delay via event channel. Hardware event feature supports hardware phase control between PWMs and duty cycle control of PWM. Each timer has two event publishers and one event subscriber. An event publisher can be used to generate a trigger to event channel, and an event subscriber can be used to receive a trigger from an event channel. Detailed information can be found from MSPM0 device's data sheet and Technical reference manual's Timer section.