SLAAER3A November   2025  – November 2025 AM2612 , AM2612-Q1 , AM263P2 , AM263P2-Q1 , AM263P4 , AM263P4-Q1 , F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Charging Inlet, DCDC, and Host Architectures and Market Trends Toward Integration
    1. 2.1 Standalone Architecture
    2. 2.2 Integration Architecture
    3. 2.3 X-in-1 Architecture
  6. 3Charging Standards Across Regions
    1. 3.1 AC Charging Inlet Standards
    2. 3.2 DC Charging Inlet Standards
  7. 4TI Automotive MCUs for Next-Generation EV Charging
    1. 4.1 MCU Selection and Requirements for Standalone Architecture
    2. 4.2 MCU Selection and Requirements for Integration Architecture
    3. 4.3 MCU Selection and Requirements for X-in-1 Architecture
  8. 5System Block Diagram of a Charging Inlet Control System
  9. 6Conclusion
  10. 7References

MCU Selection and Requirements for Standalone Architecture

Standalone architecture is more common in EU and NA regions, adapting to the CCS1, CCS2, and NACS standards with PLC communication—called the EVCC module or charging box. For some vehicles exported from Asia, the charging compatibility is achievable by adding this type of independent module.

This main task of the MCU is to assist the protocol conversion with PLC PHY, which has relatively large memory and cybersecurity requirements. The memory is occupied for charging identity recognition (EIM or PnC), openV2G, and AUTOSAR®. To support PnC (plug and charge) mode, security certificates are required to be realized by the HSM (hardware security module). Typically, around 400KB of RAM and 2M of flash storage is required for EVCC. An additional SPI, UART, or Ethernet interface, which communicates with the PLC Homeplug Green PHY, is also necessary.

The AM26x Sitara™ family of microcontrollers, incorporating the Arm® Cortex®-R5F cores, are built to meet the complex, real-time processing needs of automotive embedded products.

The AM261x-Q1 family of devices satisfy these processing requirements with the listed features:

  • Two Arm® Cortex®-R5F cores, (1 lockstep, optional) up to 400MHz (1.6K DIMPS)
  • External flash for flexible configuration, up to 1.5MB of on-chip SRAM
  • Evita-full HSM with an Arm® Cortex®-M4 core, isolated controller
  • Two CAN FD
  • Six UART
  • Four SPI
  • Three I2C
  • Three LIN
  • GPIO options on all the multiplexed pins