SLAZ345AF October   2012  – May 2021 MSP430F6731

 

  1. 1Functional Advisories
  2. 2Preprogrammed Software Advisories
  3. 3Debug Only Advisories
  4. 4Fixed by Compiler Advisories
  5. 5Nomenclature, Package Symbolization, and Revision Identification
    1. 5.1 Device Nomenclature
    2. 5.2 Package Markings
      1.      PZ100
      2.      PN80
    3. 5.3 Memory-Mapped Hardware Revision (TLV Structure)
  6. 6Advisory Descriptions
    1. 6.1  ADC39
    2. 6.2  ADC42
    3. 6.3  ADC69
    4. 6.4  AUXPMM1
    5. 6.5  AUXPMM2
    6. 6.6  BSL7
    7. 6.7  BSL14
    8. 6.8  CPU21
    9. 6.9  CPU22
    10. 6.10 CPU36
    11. 6.11 CPU40
    12. 6.12 CPU46
    13. 6.13 CPU47
    14. 6.14 DMA4
    15. 6.15 DMA7
    16. 6.16 DMA9
    17. 6.17 DMA10
    18. 6.18 EEM8
    19. 6.19 EEM17
    20. 6.20 EEM19
    21. 6.21 EEM23
    22. 6.22 JTAG26
    23. 6.23 JTAG27
    24. 6.24 LCDB5
    25. 6.25 LCDB6
    26. 6.26 PMM7
    27. 6.27 PMM11
    28. 6.28 PMM12
    29. 6.29 PMM14
    30. 6.30 PMM15
    31. 6.31 PMM18
    32. 6.32 PMM20
    33. 6.33 PMM26
    34. 6.34 PORT15
    35. 6.35 PORT19
    36. 6.36 SD3
    37. 6.37 UCS11
    38. 6.38 USCI36
    39. 6.39 USCI37
    40. 6.40 USCI41
    41. 6.41 USCI42
    42. 6.42 USCI47
    43. 6.43 USCI50
  7. 7Revision History

USCI47

USCI Module

Category

Functional

Function

eUSCI SPI slave with clock phase UCCKPH = 1

Description

The eUSCI SPI operates incorrectly under the following conditions:

1. The eUSCI_A or eUSCI_B module is configured as a SPI slave with clock phase mode UCCKPH = 1

AND

2. The SPI clock pin is not at the appropriate idle level (low for UCCKPL = 0, high for UCCKPL = 1) when the UCSWRST bit in the UCxxCTLW0 register is cleared.

If both of the above conditions are satisfied, then the following will occur:
eUSCI_A: the SPI will not be able to receive a byte (UCAxRXBUF will not be filled and UCRXIFG will not be set) and SPI slave output data will be wrong (first bit will be missed and data will be shifted).
eUSCI_B: the SPI receives data correctly but the SPI slave output data will be wrong (first byte will be duplicated or replaced by second byte).

Workaround

Use clock phase mode UCCKPH = 0 for MSP SPI slave if allowed by the application.

OR

The SPI master must set the clock pin at the appropriate idle level (low for UCCKPL = 0, high for UCCKPL = 1) before SPI slave is reset (UCSWRST bit is cleared).

OR

For eUSCI_A: to detect communication failure condition where UCRXIFG is not set, check both UCRXIFG and UCTXIFG. If UCTXIFG is set twice but UCRXIFG is not set, reset the MSP SPI slave by setting and then clearing the UCSWRST bit, and inform the SPI master to resend the data.