SLAZ755C May   2024  – November 2025 MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Functional Advisories
  5. 2Preprogrammed Software Advisories
  6. 3Debug Only Advisories
  7. 4Fixed by Compiler Advisories
  8. 5Device Nomenclature
    1. 5.1 Device Symbolization and Revision Identification
  9. 6Advisory Descriptions
    1. 6.1  ADC_ERR_05
    2. 6.2  ADC_ERR_06
    3. 6.3  AES_ERR_01
    4. 6.4  COMP_ERR_03
    5. 6.5  COMP_ERR_04
    6. 6.6  CPU_ERR_01
    7. 6.7  CPU_ERR_02
    8. 6.8  CPU_ERR_03
    9. 6.9  GPIO_ERR_03
    10. 6.10 GPIO_ERR_04
    11. 6.11 I2C_ERR_01
    12. 6.12 I2C_ERR_03
    13. 6.13 I2C_ERR_04
    14. 6.14 I2C_ERR_05
    15. 6.15 I2C_ERR_06
    16. 6.16 I2C_ERR_07
    17. 6.17 I2C_ERR_08
    18. 6.18 I2C_ERR_09
    19. 6.19 I2C_ERR_10
    20. 6.20 I2C_ERR_13
    21. 6.21 KEYSTORE_ERR_01
    22. 6.22 LCD_ERR_01
    23. 6.23 LFSS_ERR_01
    24. 6.24 LFSS_ERR_02
    25. 6.25 LFSS_ERR_03
    26. 6.26 LFXT_ERR_01
    27. 6.27 LFXT_ERR_02
    28. 6.28 PMCU_ERR_08
    29. 6.29 PMCU_ERR_09
    30. 6.30 PMCU_ERR_10
    31. 6.31 RST_ERR_01
    32. 6.32 RTC_A_ERR_02
    33. 6.33 SPI_ERR_03
    34. 6.34 SPI_ERR_04
    35. 6.35 SPI_ERR_05
    36. 6.36 SPI_ERR_06
    37. 6.37 SPI_ERR_07
    38. 6.38 SRAM_ERR_01
    39. 6.39 SYSCTL_ERR_01
    40. 6.40 SYSCTL_ERR_02
    41. 6.41 SYSCTL_ERR_03
    42. 6.42 SYSCTL_ERR_04
    43. 6.43 SYSOSC_ERR_01
    44. 6.44 TAMPERIO_ERR_01
    45. 6.45 TIMER_ERR_01
    46. 6.46 TIMER_ERR_04
    47. 6.47 TIMER_ERR_06
    48. 6.48 TIMER_ERR_07
    49. 6.49 UART_ERR_01
    50. 6.50 UART_ERR_02
    51. 6.51 UART_ERR_03
    52. 6.52 UART_ERR_04
    53. 6.53 UART_ERR_05
    54. 6.54 UART_ERR_06
    55. 6.55 UART_ERR_07
    56. 6.56 UART_ERR_08
    57. 6.57 UART_ERR_09
    58. 6.58 UART_ERR_10
    59. 6.59 UART_ERR_11
  10. 7Revision History

6.36 SPI_ERR_06

SPI Module

Category

Functional

Function

IDLE/BUSY status does not reflect the correct status of SPI IP when debug halt is asserted

Description

IDLE/BUSY is independent of halt, it is only gating the RXFIFO/TXFIFO writing/reading strobes. So, if controller is sending data, although it's not latched in FIFO but the BUSY is getting set. The POCI line transmits the previously transmitted data on the line during halt

Workaround

Don't use IDLE/BUSY status when SPI IP is halted.