The UCC5870-Q1 integrates clock monitor functions to identify clock faults during operation. The Clock monitor detects internal oscillator failures such as: oscillator clock stuck high or stuck low and clock frequency out of range. The clock monitor is enabled during a power-up event after the power-on reset is released. The clocks on both the primary side and secondary side are monitored. In the event of a clock fault on the primary side, Status is set and, if unmasked, the fault output pulls low. The primary side clock monitor has no effect on the gate driver output state. In the event of a clock fault on the secondary side, the Status is set, and the driver output is forced to the state determined by the user-set Configuration, and, if unmasked, the fault output pulls low.

The clock monitor circuit also integrates a diagnostic that checks the integrity of the monitoring circuit. The diagnostic is run automatically during the start up process. Additionally, a simulated clock monitor fault can be generated by writing to the respective Control bits for the primary or secondary sides. When enabled, the diagnostics emulates clock failure that causes a clock monitor fault. During this self-test, the actual oscillator frequency is not changed.

Additionally, UCC5870-Q1 uses a cyclic redundancy check (CRC) to ensure data integrity for the configuration of the device while the driver output is active, the SPI communications (both transmitted and received), and the internal non-volatile memory that stores the trim information ensuring the performance of the device.