SLUP412 February   2022 LMG3522R030-Q1


  1. Introduction
  2. Comparing Different Technologies
  3. Advantages of Integrating the Driver With GaN FETs
  4. The GaN-Based 6.6-kW OBC Reference Design
  5. PFC Stage
  6. DC/DC Stage
  7. DC/DC Topology Selection
  8. Frequency Selection
  9. Core Loss
  10. 10Loss of ZVS
  11. 11Dead Time
  12. 12ISR Bandwidth
  13. 13Overall
  14. 14Resonant Tank Design
  15. 15Thermal Solution
  16. 16Layout Best Practices
  17. 17Control-Loop Considerations
  18. 18Conclusions
  19. 19References
  20. 20Important Notice

DC/DC Topology Selection

In order to determine how to meet size, efficiency and output voltage regulation requirements, we evaluated two topologies in detail: the CLLLC (Figure 7-1) and the dual active bridge (DAB) (Figure 7-2).

GUID-20220218-SS0I-P3MQ-PGX9-XT2R24VFTDTN-low.png Figure 7-1 CLLLC schematic.
GUID-20220218-SS0I-HGNW-3VMX-3W2ZGNFXTBS8-low.png Figure 7-2 DAB schematic.

Both of these converters have the same fundamental structure. They both have a full bridge on the primary and secondary, and roughly the same reactive components. The fundamental differences are how the topologies are controlled, and the relative size of the reactive components.

It is beyond the scope of this paper to provide a detailed design procedure for both topologies. However, it is worth taking a look at the results of our comparison.

Figure 7-3 shows two sets of graphs: one for the CLLLC and the other for the DAB. The plot on the left shows the RMS current in the GaN switch. The plot on the right shows the GaN FET drain-to-source voltage (VDS) at turnon. These plots provide essential information on how efficient the switches will be in each topology. A low RMS current means fewer I2R losses, while a lower VDS means lower switching losses. In the end, the highest efficiency will occur when the RMS currents are as small as possible and VDS at turnon is as close to zero as possible.

GUID-20220218-SS0I-HMV7-FQSM-QSDCTFM738RG-low.png Figure 7-3 CLLLC and DAB performance comparisons.

Examining the plots in Figure 7-3 reveal that the CLLLC converter has lower RMS current when the output voltage is smaller. The reduced RMS current is critical to enabling the charger to put out as much power as possible at low voltages. Additionally, the CLLLC operates with more conditions where zero voltage switching (ZVS) is maintained.

These facts imply that the CLLLC converter will be more efficient, and therefore easier to cool. The CLLLC converter will also result in a smaller solution.