SLUUC72A September   2020  – October 2021 TPS542A50

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Before You Begin
  3. 2Description
    1. 2.1 Typical End-User Applications
    2. 2.2 EVM Features
    3. 2.3 TPS542A50EVM-059 PCB
  4. 3TPS542A50EVM-059 Bottom Circuit
    1. 3.1 Modifications
      1. 3.1.1 Output Voltage Setpoint
      2. 3.1.2 Enable and Undervoltage Lockout
      3. 3.1.3 Programming and External Clock Synchronization
      4. 3.1.4 Load Step with Function Generator
    2. 3.2 TPS542A50EVM-059 Bottom Circuit Schematic
    3. 3.3 Test Setup and Results
      1. 3.3.1  Input/Output Connections
      2. 3.3.2  Start Up Procedure
      3. 3.3.3  Electrical Performance Specifications and Results
      4. 3.3.4  Efficiency
      5. 3.3.5  Power Loss
      6. 3.3.6  Load Regulation
      7. 3.3.7  Transient Response
      8. 3.3.8  Loop Response
      9. 3.3.9  Output Voltage Ripple
      10. 3.3.10 Thermal Data
  5. 4TPS542A50EVM-059 Top Circuit (Small layout area design)
    1. 4.1 Modifications
      1. 4.1.1 Output Voltage Setpoint
      2. 4.1.2 Enable and Undervoltage Lockout
      3. 4.1.3 Programming and External Clock Synchronization
      4. 4.1.4 Load Step with Function Generator
    2. 4.2 TPS542A50EVM-059 Top Circuit (Small Layout Area) Schematic
    3. 4.3 Test Setup and Results
      1. 4.3.1  Input/Output Connections
      2. 4.3.2  Start Up Procedure
      3. 4.3.3  Electrical Performance Specifications and Results
      4. 4.3.4  Efficiency
      5. 4.3.5  Power Loss
      6. 4.3.6  Load Regulation
      7. 4.3.7  Line Regulation
      8. 4.3.8  Transient Response
      9. 4.3.9  Loop Response
      10. 4.3.10 Output Voltage Ripple
      11. 4.3.11 Start Up
  6. 5TPS542A50EVM-059 PCB Layout
  7. 6List of Materials
  8. 7Revision History

3.1.2 Enable and Undervoltage Lockout

The operation of the TPS542A50 can be enabled or disabled using J4. The EN pin of the TPS542A50 is connected to J4-2 (pin 2 of J4) and TP10. The EN pin threshold is 1.2 V. By leaving J4-2 floating, a pullup current source internal to the TPS542A50 enables the device, and the device is operational across all valid input voltages (4 V - 18 V).

Undervoltage lockout (UVLO) can be implemented by connecting a jumper between J4-2 and J4-3. In this configuration, R11 and R13 should be populated according to the TPS542A50 device data sheet based on the desired UVLO requirements. By default, R11 and R13 are not populated.

The TPS542A50 can be disabled by pulling J4-2 (the EN pin) below 1.2 V. When J4-2 is brought below 1.2 V, the regulator stop switching and enters into a low power shutdown mode. This can be accomplished in multiple ways.

The first method is to connect a control signal directly to the EN test point (TP10), referenced to AGND (TP13, TP14, or TP15, recommended between 0 V and 5.5 V). Using this method, a jumper on J4 is not necessary.

Another method is to connect a jumper between J4-1 and J4-2, and connect a control signal to J6-1, or use a TI USB-TO-GPIO connected to J6 to control the EN pin.

Default setting: J4 open, EN floating for always-on operation.

Table 3-1 Enable Pin Selection

J4 connection

 Enable Selection

J4-2 floating

 Device is enabled
J4-2 and J4-3 shorted UVLO implemented if R11 and R13 are populated - see data sheet for details

J4-1 and J4-2 shorted

Enable can be controlled with external control signal