SLVAE36A September   2018  – July 2021 LM43600 , LM43601 , LM46001 , LM46002 , LM5160A , LM5161 , LM5165 , LM5166 , LM61460-Q1 , LM73605 , LM73605-Q1 , LM73606-Q1 , LM76003 , LMR33620 , LMR33630 , LMR36006 , LMR36015 , LMZ36002 , LMZM23600 , LMZM23601 , LMZM33602 , LMZM33603 , LMZM33606 , TPS54218 , TPS54360B , TPS54418 , TPS54424 , TPS54560B , TPS54618 , TPS55010 , TPS62148 , TPS62821 , TPS62822 , TPS62823 , TPS82130 , TPS82140 , TPS82150

 

  1.   Trademarks
  2. 1Point-of-load Architecture Considerations
  3. 2Line Voltage Transients
  4. 3Thermal limitations and power budgets
  5. 4Isolation Improving Electrical Noise Immunity
  6. 5Voltage Regulation Accuracy
  7. 6Solution Size
  8. 7Complete Solution
  9. 8References
  10. 9Revision History

Point-of-load Architecture Considerations

PLCs benefit from a DC/DC point of load power solution that supports the needs of advanced analog and digital integrated circuits, offers high efficiency with good thermal performance, and reduces the overall component count and cost. Point of load strategies can vary, but PLCs are usually provided a 24-VDC input supply from the power supply or occasionally a 12-VDC input. However, the line voltage is susceptible to input voltage transients that originate from motors or relays, causing excessive voltage spike which can damage the system. Voltage spikes also come from power transmission wires routed longer distances introducing parasitic inductance loops causing problems to the DC/DC converters. It is good design practice to account for unpredictable voltage spikes by choosing a DC/DC converter that withstands an additional 50% voltage rating, or 36 V, from a 24-V rail if no other line voltage conditioning exists in the system.

In almost all cases, 5-V and 3.3-V rails are used as secondary regulation rails from 24-V or 12-V source to power low-voltage sub-systems. Since newer microcontrollers, FPGAs, memory ICs, clocks, and AFEs operate with lower voltages, it is difficult to regulate a 1-V rail with a 24-V input while switching at a higher frequency, such as 1 MHz or above, to maintain a small form factor. As shown in Equation 1, to regulate 1 V from a 24-V input (4.2% duty cycle), the minimum controllable on time of the DC/DC converter must be lower than 40 ns when switching at 1 MHz to avoid noisy pulse-skipping.

Equation 1. M i n i m u m   c o n t r o l l a b l e   o n - t i m e   =   D u t y   C y c l e S w i t c h i n g   F r e q u e n c y