If t_d(match) > 0, this means that the ON delay is larger than OFF delay. This results in truncation of a high PWM pulse by t_d(match). Conversely t_d(match) < 0 results in expansion of the high PWM pulse and truncation of the low pulse by t_d(match). Increased delay mismatch mutates the output PWM, which is why delay mismatch is also referred to as pulse-width distortion.

The actual pulse-width observed on the output can be calculated as below, where D_in is the input PWM duty cycle and f is the PWM frequency. Using min/max data sheet specifications in these calculations gives the worst case pulse-widths versus frequency as well as the range guaranteed by TI.

Figure 3-4, Figure 3-5 show the possible variation from ideal pulse width based on data sheet specifications for TPS1H100-Q1. Most devices will be well-matched and fall close to the ideal pulse-width curve, but as pulse-width decreases the output pulse-width may vary significantly for some devices.

We can then take the pulse width accuracy compared to the input and correlate this into the formula below:

From Equation 16, we know that output PWM accuracy scales proportionally with respect to frequency and inversely with respect to duty cycle. Thus, delay mismatch has the greatest distortion effect at the highest frequencies and lowest duty cycles.