SLVAFF7A december   2022  – august 2023 TPS25762-Q1 , TPS25772-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Purpose and Scope
  5. 2Firmware Boot Code Brief
  6. 3Patch Bundle Brief
  7. 4Firmware Update
    1. 4.1 Overview
    2. 4.2 EEPROM Firmware Update
      1. 4.2.1 EEPROM Memory Organization
      2. 4.2.2 EEPROM Update - 4CC Task Command Set
      3. 4.2.3 EEPROM Patch Bundle Update Process
    3. 4.3 PD Controller Patch Bundle Download
      1. 4.3.1 Patch Bundle Download - 4CC Task Command Set
      2. 4.3.2 Burst Mode Patch Download Process
  8.   Appendix A: TVSP Boot Configuration Settings
  9.   Appendix B: Using 4CC Commands
  10.   Revision History

4.2.2 EEPROM Update - 4CC Task Command Set

The 4CC ASCII commands listed in Table 4-2 need to be used when writing the patch bundle to the EEPROM from a host.

Table 4-2 4CC Task Command Set – EEPROM Update
Name of 4CC CommandASCIIInput DataX Length (In Bytes)Output DataX Length (In Bytes)Description
Secure flash update initiate commandSFWiNone3SFWi prepares the device to receive upcoming data packets. PD controller shall be in FWUP mode when this task is invoked. PD controller shall NOT perform any PD operations while in FWUP mode.
Secure flash update data commandSFWd643SFWd Task is the primary step in the Firmware Update flow. SFWd provides PD controller with the next 64- bytes to be flashed into the I2C EEPROM.
Secure Firmware Update CompleteSFWs643The SFWs Task is the final step in the Firmware Update flow provided the PD controller has been provisioned for Secure Flashing using the previous SFWx commands. SFWs passes the image signature information to the PD controller for verification of the data previously received through the SFWd Task.
Unsigned Firmware Update CompleteSFWuNone3The SFWu Task is the final step in the Firmware Update flow provided the PD controller has not been provisioned for Secure Flashing. SFWu informs the PD controller that the Firmware Update process is complete, and causes PD controller to do the verification of the image and changing of the Active Region assuming all checks pass.

To execute a 4CC Task, the host application shall follow the sequence below:

  1. If the 4CC Task requires an input, the application shall first write the input data into the DATAx (0x09 if using I2C1 or 0x11 if using I2C2) register.
  2. The application shall then write the 4CC Task characters into the corresponding CMDx (0x08 if using I2C1 or 0x10 if using I2C2) register.
  3. The application shall wait until the four byte content of the CMDx register reads the following:
  • 0x00 indicating that the command successfully executed.
  • or, !CMD indicating that the command’s execution failed.

Applications can either poll or set and use the CMDxComplete I2C event (for this application note, since the patch bundle has not been downloaded, the host can poll the state of the CMDx register).

If the task is successfully executed, the host can proceed to read the 3 bytes content of the DATAx register that contains the output data if the related task has output values.