SLVT191A May   2021  – October 2023 TPS7H1101A-SP

PRODUCTION DATA  

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Overview
  5. 2Test Procedures
  6. 3Facility
  7. 4Results
  8. 5Data Sheet Electrical Parameters and Associated Tests
  9.   A Test Results
  10.   B Revision History

5 Data Sheet Electrical Parameters and Associated Tests

1.5 V ≤ VIN ≤ 7 V, VOUT(target) = VIN – 0.35 V, IOUT = 10 mA, VEN = 1.1 V, COUT = 22 μF, PG terminal pulled up to VIN with 50 kΩ, over operating temperature range (TJ = –55°C to 125°C), unless otherwise noted. Typical values are at TJ = 25°C.

ParametersTest ConditionsMINTYPMAXUnitTest Numbers
SymbolDescription
VINInput Voltage Range1.57V13.1, 13.2
VFBFeedback pin voltage(1)0 A ≤ IOUT ≤ 3 A, 1.5 V ≤ VIN ≤ 7 V0.5940.6050.616V13.0, 13.16, 13.17, 25.16, 25.17, 25.19, 25.20, 25.22, 25.23
VOUTOutput voltage range0.8VINV13.1, 13.2, 13.4
Output voltage accuracy(1)0 A ≤ IOUT ≤ 3 A, 1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, 1.2 V, 1.8 V, 6.65 V–22%13.1, 13.10, 13.11, 13.13, 13.14, 13.2, 13.4, 25.0, 25.1, 25.10, 25.12, 25.14, 25.4, 25.5, 25.7, 25.8, 28.4, 28.5, 28.7, 28.8
ΔVOUT%/ ΔVINLine regulation1.5 V ≤ VIN ≤ 7 V–0.070.010.07% / V13.12, 13.15, 13.3
ΔVOUTDC input line regulation1.5 V ≤ VIN ≤ 7 V, VOUT = 0.8 V, IOUT = 10 mA, TJ = 25°C(2)0.20.6mV13.19
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.2 V, IOUT = 10 mA, TJ = 25°C(2)0.20.6mV13.21
1.5 V ≤ VIN ≤ 7 V, VOUT = 1.8 V, IOUT = 10 mA, TJ = 25°C(2)0.20.6mV13.20
VDODropout voltage(3)IOUT = 3 A, VOUT = 1.3 V, VIN = VOUT + VDO210335mV13.6
ICLProgrammable output current limit rangeVIN = 1.5 V, VOUT = 1.2 V, PCL resistance = 47 kΩ500750mA26.1
VIN = 1.5 V, VOUT = 1.2 V, PCL resistance varies2003500(4)mA26.0
CSRCurrent sense ratioLOAD / ICS, VIN = 2.3 V, VOUT = 1.9 V, TJ = 25°C, ILOAD ≥ 500 mA4500059000A/A20.3, 20.7, 20.9
IGNDGND pin currentVIN = 1.5 V, VOUT = 1.2 V, IOUT = 2 A1016mA13.8
IQQuiescent current (no load)VIN = VOUT + 0.5 V, IOUT = 0 A710mA12.0, 12.1, 12.2, 12.3
ISHDNShutdown current (IGND)1.5 V ≤ VIN ≤ 7 V, TJ = 25°C(6)26230µA11.0, 11.1, 11.2, 11.3
ISNS, IFBFB/SNS pin currentVIN = 7 V, VOUT = 6.65 V15nA19.0
IENEN pin input currentVIN = 7 V, VEN = 7 V, VOUT = 6.65 V20150nA14.3, 15.3, 25.2, 28.2
VILENEN pin input low (disable)1.5 V < VIN < 7 V0.55V14.0, 15.0, 16.0
VIHENEN pin input high (enable)3.5 V < VIN < 7 VVIN - 0.7V14.1, 15.1, 16.1
Eprop DlyEnable pin propagation delayVIN = 2.2 V, EN rise to IOUTrise6501000uS20.1
TENEnable pin turn-on delay

(Delay to PG assertion)

VIN = 2.2 V, VOUT = 1.8 V, ILoad = 0.5 A, COUT = 220 µF, CSS = 2 nF1.41.6mS20.0
VTHPGPG threshold onNo load, 0.8 V ≤ VOUT ≤ 6.65 V8690%17.1, 17.5
VTHPGHYSPG hysteresis1.5 V ≤ VIN ≤ 7 V2%22.9
VOL PGPG pin output lowIPG = 0 mA to –1 mA120300mV17.2, 17.3
ILKGPGPG pin leakage currentVOUT > VTHPG, VPG = 1.2 V0.21.5μA23.0
VOUT > VTHPG, VPG = 7 V0.52.5μA
ISSSS terminal Charge currentVIN = 1.5 V to 7 V2.53.5μA21.0, 22.0
VSSSS terminal voltage (device enabled)(7)VIN = 1.5 V to 7 V1.232V22.1
  1. The output voltage accuracy of condition at IOUT = 2 A and IOUT = 3 A is specified by characterization, but not production tested.
  2. Line and load regulations done under pulse condition for t < 10 ms.
  3. The parameter is specified to the limit in characterization, but not production tested.
  4. The maximum limit of the ICL parameter is specified to the limit in characterization, but not production tested.
  5. To make sure that foldback is enabled, VCS must be > 0.9 × VFB.
  6. This maximum limit applies to SMD 5962R13202 post 100-krad(Si) test at 25°C.
  7. Any external pullup voltage must not exceed 1.188 V.