SLVUB50C June   2017  – March 2019 UCD90120A , UCD90124A , UCD90160 , UCD90160A , UCD90240 , UCD90320 , UCD90320U , UCD9090 , UCD9090-Q1 , UCD9090A , UCD90910

 

  1.   UCD90xxx Sequencer Schematics Guidelines
    1. 1 Introduction
    2. 2 UCD Power Supply Review
      1. 2.1 UCD90240, UCD90320 and UCD90320U
      2. 2.2 Remaining UCD90xxx Devices
    3. 3 I/O Signals Review
      1. 3.1 Analog Monitor (MONx/AMONx) Pin Review
      2. 3.2 PMBUS Signals Review
      3. 3.3 GPIO Pins Review
      4. 3.4 Margin Pins Review
      5.      Trademarks
  2.   Revision History

3.4 Margin Pins Review

It is a good design practice to provide a series impedance of 20 Ω to 33 Ω at the signal source to slow fast digital edges and route FPWM signals away from sensitive analog signals when they are used for fan control or margining function. Consult Design Voltage Margining Circuit for UCD90xxx Power Sequencer and System Manager (SLVA845) for margining circuit design and UCD90xxx Voltage Margining Circuit Design Tool (SLVC676).