SLVUBT8B November   2020  – June 2022 LP8764-Q1 , TPS6594-Q1

 

  1.   Scalable PMIC's GUI User’s Guide
  2.   Trademarks
  3. 1 Introduction
  4. 2 Supported Features
  5. 3 Revisions
  6. 4 Overview
  7. 5 Getting Started
    1. 5.1 Finding the GUI
    2. 5.2 Downloading the Required Software
    3. 5.3 Launching the GUI
    4. 5.4 Connecting to a PMIC
  8. 6 Quick-start Page
    1. 6.1 Device Scan Results
    2. 6.2 Configuration and Monitoring
      1. 6.2.1 System Info
      2. 6.2.2 BUCK
      3. 6.2.3 LDO
      4. 6.2.4 GPIO
      5. 6.2.5 Interrupts
      6. 6.2.6 Miscellaneous Settings
      7. 6.2.7 Advanced
  9. 7 Register Map Page
  10. 8 NVM Configuration Page
    1. 8.1 Creating a Custom Configuration
      1. 8.1.1 Static Configuration
      2. 8.1.2 Pre-Configurable Mission States (PFSM)
        1. 8.1.2.1 Creating a State Diagram
        2. 8.1.2.2 Global Settings
        3. 8.1.2.3 Power Sequence
          1. 8.1.2.3.1 Power Sequence Resources and Commands
          2. 8.1.2.3.2 Sub-sequences
          3. 8.1.2.3.3 Power Sequence Editing Tools
        4. 8.1.2.4 Trigger Settings
        5. 8.1.2.5 Trigger Priority List
        6. 8.1.2.6 PFSM Validation
    2. 8.2 Program
      1. 8.2.1 Program an Existing NVM Configuration
      2. 8.2.2 NVM Configuration Special Use Case: Changing the Communication Interface
      3. 8.2.3 Lock Option During NVM Programming
  11. 9 NVM Validation Page
  12. 10Watchdog Page
  13. 11Additional Resources
  14. 12Appendix A: Troubleshooting
    1. 12.1 Hardware Platform Not Recognized
    2. 12.2 PMIC Device Not Found
    3. 12.3 I2C2 is configured but not connected
  15. 13Appendix B: Advanced Topics
    1. 13.1 Scripting Window
  16. 14Appendix C: Known Limitations
  17. 15Appendix D: Migration Topics
    1. 15.1 Migrating from LP8764-Q1 PG1.0 to PG2.0
    2. 15.2 Update the PFSM to Include the PFSM_START State
    3. 15.3 Update Timing Delays
    4. 15.4 Update Trigger Priority and Settings
  18. 16Revision History

3 Revisions

This section details the features added with each release of the Scalable PMIC's GUI. Section 14 also lists known issues for each version.

Release 1.0.0 is the initial pre-production release and named the Programmable Processor PMIC's GUI. This version of the tool allows for evaluation and programming but does not provide a mechanism to create NVM configurations.

Release 2.0.0 built upon the features of release 1.0.0, specifically adding the NVM Configuration, NVM Validation, and WatchDog evaluation pages.

Release 3.0.0 is the latest release and named the Scalable PMIC's GUI. This document reflects this latest version.

Table 3-1 GUI Revisions
Revision Release Date Devices Supported Feature Updates and Additions
1.0.0 December 2019
  • TPS6594-Q1 Revision 1.0 Silicon
 Initial Pre-Production Release
  • Quick-start Page
  • Register Map Page
  • NVM Programming
2.0.0 November 2020
  • TPS6594-Q1
  • LP8764-Q1 Revision 1.0 Silicon
  • TPS6593-Q1
  • TPS6594-Q1 Revision 1.0 Silicon
  • NVM Creation and validation
  • NVM Templates
  • Scripting
  • LP8764-Q1 Device Support
  • Improved programming speed
  • Watchdog Evaluation Page
  • SPI and CRC enabled serial communication
  • Automated Timing adjustements to meet desired delay times.
3.0.0 June 2022
  • TPS6594-Q1
  • LP8764-Q1 Revision 2.0 Silicon
  • TPS6593-Q1
  • LP8762-Q1
  • LP876242-Q1
  • NVM Creation updated to allow for more flexibility in NVM design.
  • More feedback mechanisms to identify potential NVM issues.
  • Multi-SPI Communication controls Chip Select for all PMICs on the SPI bus.
  • Improved transitions between pages.
  • Removed automated timing adjustments to meet desired delay times.
  • Added Validation errors and instructions to manually control delay timing.