SLVUBX4A November   2020  – February 2022 LP8764-Q1


  1.   Trademarks
  2. 1Introduction
  3. 2Getting Started
    1. 2.1 Getting Started: Single EVM
    2. 2.2 Getting Started: Multiple EVM Evaluation
    3. 2.3 GUI Tool
  4. 3EVM Details
    1. 3.1 Terminal Blocks
    2. 3.2 Test Point Descriptions
    3. 3.3 Configuration Headers
    4. 3.4 Stack-up Headers
    5. 3.5 Connectors
    6. 3.6 Dip Switches
    7. 3.7 EVM Control and GPIO
  5. 4Customization
    1. 4.1 Changing the Communication Interface
    2. 4.2 Changing the Phase Configuration
  6. 5Schematic, Layout, and Bill of Materials
  7. 6Additional Resources
  8. 7Revision History

Test Point Descriptions

Numerous test points are provided to access voltages and signals. Test points marked with _S are designed for sensing voltages only and are not designed to carry large DC currents.

Table 3-2 Test Point Descriptions
Test PointDevice PinDescription
TP1VCCA_SVCCA voltage sense point. Routed from close to the VCCA pin of the LP8764-Q1.
TP2, TP4, TP6, TP7, TP8, TP9, TP10GND_SGround sense points routed from various locations.
TP3VOUT_LDO_SVoltage sense point for the internal LDO output voltage.
TP5VIO_SVIO voltage sense routed from the VIO pin of the LP8764-Q1.
TP11, TP12, TP13, TP14, TP15, TP16GND Solid ground points. Are able to carry larger DC currents.
J14, J16, J17, J19 FB_B1, FB_B2, FB_B3, FB_B4 Buck output voltage sense points. Secondary buck unused FBs are possible to use as voltage monitor as well.