SLVUC05A November   2020  – July 2022 TPS25750


  1.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documents
    5.     Support Resources
    6.     Trademarks
  2. 1Introduction
    1. 1.1 Introduction
      1. 1.1.1 Purpose and Scope
    2. 1.2 PD Controller Host Interface Description
      1. 1.2.1 Overview
      2. 1.2.2 Register and Field Notation
    3. 1.3 Unique Address Interface
      1. 1.3.1 Unique Address Interface Protocol
      2. 1.3.2 Unique Address Interface Registers
  3. 2Unique Address Interface Register Detailed Descriptions
    1. 2.1  0x03 MODE Register
    2. 2.2  0x0D DEVICE_CAPABILITIES Register
    3. 2.3  0x14 - 0x19 INT_EVENT, INT_MASK, INT_CLEAR Registers
    4. 2.4  0x1A STATUS Register
    5. 2.5  0x26 POWER_PATH_STATUS Register
    6. 2.6  0x29 PORT_CONTROL Register
    7. 2.7  0x2D BOOT_STATUS Register
    8. 2.8  0x30 RX_SOURCE_CAPS Register
    9. 2.9  0x31 RX_SINK_CAPS Register
    10. 2.10 0x32 TX_SOURCE_CAPS Register
    11. 2.11 0x33 TX_SINK_CAPS Register
    12. 2.12 0x34 ACTIVE_CONTRACT_PDO Register
    13. 2.13 0x35 ACTIVE_CONTRACT_RDO Register
    14. 2.14 0x3F POWER_STATUS Register
    15. 2.15 0x40 PD_STATUS Register
    16. 2.16 GPIO Events
    17. 2.17 0x69 TYPEC_STATE Register
    18. 2.18 0x70 SLEEP_CONFIG Register
    19. 2.19 0x72 GPIO_STATUS Register
  4. 34CC Task Detailed Descriptions
    1. 3.1 Overview
    2. 3.2 PD Message Tasks
      1. 3.2.1 'SWSk' - PD PR_Swap to Sink
      2. 3.2.2 'SWSr' - PD PR_Swap to Source
      3. 3.2.3 'SWDF' - PD DR_Swap to DFP
      4. 3.2.4 'SWUF' - PD DR_Swap to UFP
      5. 3.2.5 'GSkC' - PD Get Sink Capabilities
      6. 3.2.6 'GSrC' - PD Get Source Capabilities
      7. 3.2.7 'SSrC' - PD Send Source Capabilities
    3. 3.3 Patch Bundle Update Tasks
      1. 3.3.1 'PBMs' - Start Patch Burst Mode Download Sequence
      2. 3.3.2 'PBMc' - Patch Burst Mode Download Complete
      3. 3.3.3 'PBMe' - End Patch Burst Mode Download Sequence
      4. 3.3.4 Patch Burst Mode Example
      5. 3.3.5 'GO2P' - Go to Patch Mode
    4. 3.4 System Tasks
      1. 3.4.1 'DBfg' - Clear Dead Battery Flag
      2. 3.4.2 'I2Cr' - I2C Read Transaction
      3. 3.4.3 'I2Cw' - I2C Write Transaction
  5. 4User Reference
    1. 4.1 PD Controller Application Customization
    2. 4.2 Loading a Patch Bundle
  6. 5Revision History

0x1A STATUS Register

Table 2-8 0x1A STATUS Register
AddressNameAccessLengthUnique Per PortPower-Up Default
0x1ASTATUSRO5yesNever fully reset though many bits change during disconnect and connect.
Table 2-9 0x1A STATUS Register Bit Field Definitions
Byte 5:
7:0 Reserved
Bytes 1-4:
30:28 Reserved
27 Bist Indicates if a BIST procedure is in progress.
0b No BIST in progress.
1b BIST in progress. This may also be indicated by MODE register (0x03) reading 'BIST'.
26 Reserved
25:24 ActingAsLegacy Indicates when PD Controller has gone into a mode where it is acting like a legacy (non PD) device. It can take approximately 10 seconds for the PD controller to determine that it is attached to a legacy source or sink.
00b PD Controller is not in a legacy (non PD) mode
01b PD Controller is acting like a legacy sink. It will not respond to USB PD message traffic.
10b PD Controller is acting like a legacy source. It will not respond to USB PD message traffic.
11b PD controller is acting as a legacy sink (non-PD) port until the dead battery flag is cleared. The PD controller enters this state if no Source Capabilities are received after the boot process is complete. After the dead-battery flag is cleared, the PD controller will send a Hard Reset.
23:22 UsbHostPresent USB host attachment status.
00b No host present. This means that no far-end device is presently providing VBUS or the PD Controller power role is Source.
01b VBUS is being provided by a Port Partner that is a PD device not capable of USB communications.
10b VBUS is being provided by a Port Partner that is not a PD device.
11b Host present. This means VBUS is being provided by a Port Partner that is USB PD capable and also capable of USB communications.
21:20 VbusStatus Indicates the present state of VBUS.
00b At vSafe0V (less than 0.8V)
01b At vSafe5V (4.75 V to 5.5 V).
10b Within expected limits. The limits are determined based on the USB PD negotiated value.
11b Not within any of the other specified ranges.
19:7 Reserved
6 DataRole PD controller data role. This is only valid after there is a connection.
0b Upward-facing port (UFP)
1b Downward-facing port (DFP)
5 PortRole Current state of PD Controller CCx terminations. This also indicates the PD Controller Power Role, after connected. This bit does not toggle during Unattached.* state transitions.
0b PD Controller is in the Sink role. This means the CCx pull-down is active or the port is disabled/disconnected.
1b PD Controller is Source (CCx pull-up active).
4 PlugOrientation Plug orientation indicator. Indicates port orientation when known (requires connection).
0b Upside-up orientation (plug CC on CC1). Can also be an unknown orientation or the port may be disabled/disconnected.
1b Upside-down orientation (plug CC on CC2).
3:1 ConnState Details of a connected plug.
000b No connection.
001b Port is disabled.
010b Audio connection (Ra/Ra).
011b Debug connection (Rd/Rd).
100b No connection, Ra detected (Ra but no Rd).
101b Reserved (may be used for Rp/Rp Debug connection).
110b Connection present, no Ra detected. Can be an Rd (but no Ra) or an Rp detected with no previous Ra detection, includes PD Controller that connected in Attached.SNK.
111b Connection present, Ra detected. Can be Rd (and Ra) detected or Rp detected (with previous Ra detection, if the PD Controller started as Source and later swapped to Sink).
0 PlugPresent Status of the plug
0b No plug is connected.
1b A plug is connected.
This feature is not supported by TPS25750_F509.04.02.
This feature is not supported by TPS25750_F509.04.02.
This feature is not supported by TPS25750_F509.05.02.